clock24coms.vhd

来自「这是一个数字时钟的Verilog程序 仿真通过 能实现秒 分 时 计时」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE clock24coms IS
COMPONENT jsq60
   PORT(clk:IN STD_LOGIC;
        en0,en1,cin:IN STD_LOGIC;
        datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        co:OUT STD_LOGIC;
        q0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        q1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT jsq24
   PORT(clk:IN STD_LOGIC;
        en0,en1,cin:IN STD_LOGIC;
        datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        co:OUT STD_LOGIC;
        q0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        q1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT decoder
   PORT(datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
             y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
END PACKAGE;