decoder.vhd

来自「这是一个数字时钟的Verilog程序 仿真通过 能实现秒 分 时 计时」· VHDL 代码 · 共 31 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY decoder IS
   PORT(datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
             y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END decoder;
ARCHITECTURE rtl OF decoder IS
  SIGNAL sd:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
    sd<=datain;
    PROCESS(sd)
     BEGIN
        CASE sd IS
           WHEN"0000"=>y<="11111110";
           WHEN"0001"=>y<="10110000";
           WHEN"0010"=>y<="11101101";
           WHEN"0011"=>y<="11111001";
           WHEN"0100"=>y<="10110011";
           WHEN"0101"=>y<="11011011";
           WHEN"0110"=>y<="11011111";
           WHEN"0111"=>y<="11110000";
           WHEN"1000"=>y<="11111111";
           WHEN"1001"=>y<="11111011";
           WHEN OTHERS=>y<="11111110";
         END CASE;
   END PROCESS;
END rtl;