_info

verilog 编写的pic16c5x时钟模块

m255
cModel Technology
de:\fpga\clkgen
vclkgen
Ikl:Ehn>L_z]@ddz:UM5^J3
Vm`kXK9cjiEN=??KfM;lOO2
dE:\fpga\clkgen
w1179497926
Fclkgen.v
L0 1
OE;L;5.7c;17
r1
31
vglbl
I;3bdO6U;R_i?oXm0zZ=6m3
V]6_PH00iDgcD`AVz9`gA:0
dE:\fpga\clkgen
w1074187860
FC:/Xilinx/verilog/src/glbl.v
L0 5
OE;L;5.7c;17
r1
31
vwave
I@hzfj>O5>fEBAU@f6Rloc2
Vm=]fSh[8g7W4?hJN<m=X[3
dE:\fpga\clkgen
w1179498084
Fwave.tfw
L0 16
OE;L;5.7c;17
r1
31
vWAVE
I>kD8TOAe_KQVBTR_=Vb432
Vm=]fSh[8g7W4?hJN<m=X[3
dE:\fpga\clkgen
w1175744092
Fwave.ant
L0 8
OE;L;5.7c;17
r1
31
n@w@a@v@e