b8_adder.fit.qmsg

8位的加法器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 12 16:22:19 2006 " "Info: Processing started: Thu Oct 12 16:22:19 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off b8_adder -c b8_adder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off b8_adder -c b8_adder" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "b8_adder EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"b8_adder\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "26 26 " "Info: No exact pin location assignment(s) for 26 pins of 26 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r0 " "Info: Pin r0 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r0" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r0 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r1 " "Info: Pin r1 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r1" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r1 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r2 " "Info: Pin r2 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r2" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r2 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r3 " "Info: Pin r3 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r3" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r3 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r4 " "Info: Pin r4 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r4" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r4 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r4 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r5 " "Info: Pin r5 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r5" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r5 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r5 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r6 " "Info: Pin r6 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r6" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r6 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r6 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r7 " "Info: Pin r7 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r7" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { r7 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { r7 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "c7 " "Info: Pin c7 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "c7" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { c7 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { c7 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "c_1 " "Info: Pin c_1 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "c_1" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { c_1 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { c_1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b0 " "Info: Pin b0 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b0" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b0 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a0 " "Info: Pin a0 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a0" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a0 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b1 " "Info: Pin b1 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b1" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b1 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a1 " "Info: Pin a1 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a1" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a1 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b2 " "Info: Pin b2 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b2" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b2 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a2 " "Info: Pin a2 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a2" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a2 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b3 " "Info: Pin b3 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b3" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b3 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a3 " "Info: Pin a3 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a3" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a3 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b4 " "Info: Pin b4 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b4" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b4 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b4 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a4 " "Info: Pin a4 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a4" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a4 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a4 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b5 " "Info: Pin b5 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b5" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b5 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b5 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a5 " "Info: Pin a5 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a5" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a5 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a5 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b6 " "Info: Pin b6 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b6" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b6 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b6 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a6 " "Info: Pin a6 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a6" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a6 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a6 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "b7 " "Info: Pin b7 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "b7" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { b7 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { b7 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "a7 " "Info: Pin a7 not assigned to an exact location on the device" {  } { { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "a7" } } } } { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { a7 } "NODE_NAME" } "" } } { "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" { Floorplan "E:/JACK/VHDL/b8_adder/b8_adder.fld" "" "" { a7 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}