b8_adder.tan.qmsg

8位的加法器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 12 16:22:27 2006 " "Info: Processing started: Thu Oct 12 16:22:27 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off b8_adder -c b8_adder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off b8_adder -c b8_adder --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "c_1 r7 17.145 ns Longest " "Info: Longest tpd from source pin \"c_1\" to destination pin \"r7\" is 17.145 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns c_1 1 PIN PIN_118 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_118; Fanout = 2; PIN Node = 'c_1'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "" { c_1 } "NODE_NAME" } "" } } { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.072 ns) + CELL(0.442 ns) 6.989 ns f_adder:mo\|ior2:m2\|z~69 2 COMB LC_X32_Y1_N6 2 " "Info: 2: + IC(5.072 ns) + CELL(0.442 ns) = 6.989 ns; Loc. = LC_X32_Y1_N6; Fanout = 2; COMB Node = 'f_adder:mo\|ior2:m2\|z~69'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "5.514 ns" { c_1 f_adder:mo|ior2:m2|z~69 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.114 ns) 7.536 ns f_adder:m1\|ior2:m2\|z~128 3 COMB LC_X32_Y1_N2 2 " "Info: 3: + IC(0.433 ns) + CELL(0.114 ns) = 7.536 ns; Loc. = LC_X32_Y1_N2; Fanout = 2; COMB Node = 'f_adder:m1\|ior2:m2\|z~128'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "0.547 ns" { f_adder:mo|ior2:m2|z~69 f_adder:m1|ior2:m2|z~128 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 8.278 ns f_adder:m2\|ior2:m2\|z~177 4 COMB LC_X32_Y1_N9 2 " "Info: 4: + IC(0.450 ns) + CELL(0.292 ns) = 8.278 ns; Loc. = LC_X32_Y1_N9; Fanout = 2; COMB Node = 'f_adder:m2\|ior2:m2\|z~177'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "0.742 ns" { f_adder:m1|ior2:m2|z~128 f_adder:m2|ior2:m2|z~177 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.885 ns) + CELL(0.114 ns) 11.277 ns f_adder:m3\|ior2:m2\|z~69 5 COMB LC_X9_Y1_N1 2 " "Info: 5: + IC(2.885 ns) + CELL(0.114 ns) = 11.277 ns; Loc. = LC_X9_Y1_N1; Fanout = 2; COMB Node = 'f_adder:m3\|ior2:m2\|z~69'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "2.999 ns" { f_adder:m2|ior2:m2|z~177 f_adder:m3|ior2:m2|z~69 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.114 ns) 11.830 ns f_adder:m4\|ior2:m2\|z~69 6 COMB LC_X9_Y1_N5 2 " "Info: 6: + IC(0.439 ns) + CELL(0.114 ns) = 11.830 ns; Loc. = LC_X9_Y1_N5; Fanout = 2; COMB Node = 'f_adder:m4\|ior2:m2\|z~69'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "0.553 ns" { f_adder:m3|ior2:m2|z~69 f_adder:m4|ior2:m2|z~69 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.114 ns) 12.387 ns f_adder:m5\|ior2:m2\|z~69 7 COMB LC_X9_Y1_N3 2 " "Info: 7: + IC(0.443 ns) + CELL(0.114 ns) = 12.387 ns; Loc. = LC_X9_Y1_N3; Fanout = 2; COMB Node = 'f_adder:m5\|ior2:m2\|z~69'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "0.557 ns" { f_adder:m4|ior2:m2|z~69 f_adder:m5|ior2:m2|z~69 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.114 ns) 12.941 ns f_adder:m6\|ior2:m2\|z~69 8 COMB LC_X9_Y1_N6 2 " "Info: 8: + IC(0.440 ns) + CELL(0.114 ns) = 12.941 ns; Loc. = LC_X9_Y1_N6; Fanout = 2; COMB Node = 'f_adder:m6\|ior2:m2\|z~69'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "0.554 ns" { f_adder:m5|ior2:m2|z~69 f_adder:m6|ior2:m2|z~69 } "NODE_NAME" } "" } } { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.114 ns) 13.483 ns f_adder:m7\|h_adder:m1\|r 9 COMB LC_X9_Y1_N2 1 " "Info: 9: + IC(0.428 ns) + CELL(0.114 ns) = 13.483 ns; Loc. = LC_X9_Y1_N2; Fanout = 1; COMB Node = 'f_adder:m7\|h_adder:m1\|r'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "0.542 ns" { f_adder:m6|ior2:m2|z~69 f_adder:m7|h_adder:m1|r } "NODE_NAME" } "" } } { "../h_adder/h_adder.vhd" "" { Text "E:/JACK/VHDL/h_adder/h_adder.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.554 ns) + CELL(2.108 ns) 17.145 ns r7 10 PIN PIN_81 0 " "Info: 10: + IC(1.554 ns) + CELL(2.108 ns) = 17.145 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'r7'" {  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "3.662 ns" { f_adder:m7|h_adder:m1|r r7 } "NODE_NAME" } "" } } { "b8_adder.vhd" "" { Text "E:/JACK/VHDL/b8_adder/b8_adder.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.001 ns 29.17 % " "Info: Total cell delay = 5.001 ns ( 29.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.144 ns 70.83 % " "Info: Total interconnect delay = 12.144 ns ( 70.83 % )" {  } {  } 0}  } { { "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/b8_adder/db/b8_adder_cmp.qrpt" Compiler "b8_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/b8_adder/db/b8_adder.quartus_db" { Floorplan "E:/JACK/VHDL/b8_adder/" "" "17.145 ns" { c_1 f_adder:mo|ior2:m2|z~69 f_adder:m1|ior2:m2|z~128 f_adder:m2|ior2:m2|z~177 f_adder:m3|ior2:m2|z~69 f_adder:m4|ior2:m2|z~69 f_adder:m5|ior2:m2|z~69 f_adder:m6|ior2:m2|z~69 f_adder:m7|h_adder:m1|r r7 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.145 ns" { c_1 c_1~out0 f_adder:mo|ior2:m2|z~69 f_adder:m1|ior2:m2|z~128 f_adder:m2|ior2:m2|z~177 f_adder:m3|ior2:m2|z~69 f_adder:m4|ior2:m2|z~69 f_adder:m5|ior2:m2|z~69 f_adder:m6|ior2:m2|z~69 f_adder:m7|h_adder:m1|r r7 } { 0.000ns 0.000ns 5.072ns 0.433ns 0.450ns 2.885ns 0.439ns 0.443ns 0.440ns 0.428ns 1.554ns } { 0.000ns 1.475ns 0.442ns 0.114ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 0.114ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 12 16:22:27 2006 " "Info: Processing ended: Thu Oct 12 16:22:27 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}