b8_adder.fit.eqn

8位的加法器设计

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C61L1 is f_adder:mo|h_adder:m1|r~14 at LC_X32_Y1_N5
--operation mode is normal

C61L1 = c_1 $ b0 $ a0;


--D8L1 is f_adder:mo|ior2:m2|z~69 at LC_X32_Y1_N6
--operation mode is normal

D8L1 = c_1 & (b0 # a0) # !c_1 & b0 & a0;


--C2_r is f_adder:m1|h_adder:m1|r at LC_X32_Y1_N8
--operation mode is normal

C2_r = b1 $ (a1 $ D8L1);


--D1L1 is f_adder:m1|ior2:m2|z~128 at LC_X32_Y1_N2
--operation mode is normal

D1L1 = b1 & (a1 # D8L1) # !b1 & (a1 & D8L1);


--C4_r is f_adder:m2|h_adder:m1|r at LC_X32_Y1_N4
--operation mode is normal

C4_r = b2 $ D1L1 $ a2;


--D2L1 is f_adder:m2|ior2:m2|z~177 at LC_X32_Y1_N9
--operation mode is normal

D2L1 = b2 & (D1L1 # a2) # !b2 & D1L1 & a2;


--C6_r is f_adder:m3|h_adder:m1|r at LC_X9_Y1_N4
--operation mode is normal

C6_r = b3 $ (a3 $ D2L1);


--D3L1 is f_adder:m3|ior2:m2|z~69 at LC_X9_Y1_N1
--operation mode is normal

D3L1 = b3 & (a3 # D2L1) # !b3 & (a3 & D2L1);


--C8_r is f_adder:m4|h_adder:m1|r at LC_X9_Y1_N9
--operation mode is normal

C8_r = b4 $ (a4 $ D3L1);


--D4L1 is f_adder:m4|ior2:m2|z~69 at LC_X9_Y1_N5
--operation mode is normal

D4L1 = b4 & (a4 # D3L1) # !b4 & (a4 & D3L1);


--C01_r is f_adder:m5|h_adder:m1|r at LC_X9_Y1_N8
--operation mode is normal

C01_r = a5 $ (b5 $ D4L1);


--D5L1 is f_adder:m5|ior2:m2|z~69 at LC_X9_Y1_N3
--operation mode is normal

D5L1 = a5 & (b5 # D4L1) # !a5 & (b5 & D4L1);


--C21_r is f_adder:m6|h_adder:m1|r at LC_X9_Y1_N0
--operation mode is normal

C21_r = b6 $ (a6 $ D5L1);


--D6L1 is f_adder:m6|ior2:m2|z~69 at LC_X9_Y1_N6
--operation mode is normal

D6L1 = b6 & (a6 # D5L1) # !b6 & (a6 & D5L1);


--C41_r is f_adder:m7|h_adder:m1|r at LC_X9_Y1_N2
--operation mode is normal

C41_r = b7 $ a7 $ D6L1;


--D7L1 is f_adder:m7|ior2:m2|z~67 at LC_X9_Y1_N7
--operation mode is normal

D7L1 = b7 & (a7 # D6L1) # !b7 & a7 & D6L1;


--c_1 is c_1 at PIN_118
--operation mode is input

c_1 = INPUT();


--b0 is b0 at PIN_117
--operation mode is input

b0 = INPUT();


--a0 is a0 at PIN_122
--operation mode is input

a0 = INPUT();


--b1 is b1 at PIN_114
--operation mode is input

b1 = INPUT();


--a1 is a1 at PIN_121
--operation mode is input

a1 = INPUT();


--b2 is b2 at PIN_120
--operation mode is input

b2 = INPUT();


--a2 is a2 at PIN_115
--operation mode is input

a2 = INPUT();


--b3 is b3 at PIN_82
--operation mode is input

b3 = INPUT();


--a3 is a3 at PIN_74
--operation mode is input

a3 = INPUT();


--b4 is b4 at PIN_67
--operation mode is input

b4 = INPUT();


--a4 is a4 at PIN_78
--operation mode is input

a4 = INPUT();


--b5 is b5 at PIN_76
--operation mode is input

b5 = INPUT();


--a5 is a5 at PIN_85
--operation mode is input

a5 = INPUT();


--b6 is b6 at PIN_60
--operation mode is input

b6 = INPUT();


--a6 is a6 at PIN_28
--operation mode is input

a6 = INPUT();


--b7 is b7 at PIN_29
--operation mode is input

b7 = INPUT();


--a7 is a7 at PIN_80
--operation mode is input

a7 = INPUT();


--r0 is r0 at PIN_108
--operation mode is output

r0 = OUTPUT(C61L1);


--r1 is r1 at PIN_116
--operation mode is output

r1 = OUTPUT(C2_r);


--r2 is r2 at PIN_113
--operation mode is output

r2 = OUTPUT(C4_r);


--r3 is r3 at PIN_73
--operation mode is output

r3 = OUTPUT(C6_r);


--r4 is r4 at PIN_75
--operation mode is output

r4 = OUTPUT(C8_r);


--r5 is r5 at PIN_77
--operation mode is output

r5 = OUTPUT(C01_r);


--r6 is r6 at PIN_79
--operation mode is output

r6 = OUTPUT(C21_r);


--r7 is r7 at PIN_81
--operation mode is output

r7 = OUTPUT(C41_r);


--c7 is c7 at PIN_68
--operation mode is output

c7 = OUTPUT(D7L1);