f_adder.tan.qmsg

8位的加法器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 22 15:56:56 2006 " "Info: Processing started: Fri Sep 22 15:56:56 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off f_adder -c f_adder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off f_adder -c f_adder --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ain rout 10.009 ns Longest " "Info: Longest tpd from source pin \"ain\" to destination pin \"rout\" is 10.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ain 1 PIN PIN_180 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 2; PIN Node = 'ain'" {  } { { "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" Compiler "f_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/f_adder/db/f_adder.quartus_db" { Floorplan "E:/JACK/VHDL/f_adder/" "" "" { ain } "NODE_NAME" } "" } } { "f_adder.vhd" "" { Text "E:/JACK/VHDL/f_adder/f_adder.vhd" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.592 ns) + CELL(0.590 ns) 6.651 ns h_adder:m1\|r~14 2 COMB LC_X34_Y20_N4 1 " "Info: 2: + IC(4.592 ns) + CELL(0.590 ns) = 6.651 ns; Loc. = LC_X34_Y20_N4; Fanout = 1; COMB Node = 'h_adder:m1\|r~14'" {  } { { "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" Compiler "f_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/f_adder/db/f_adder.quartus_db" { Floorplan "E:/JACK/VHDL/f_adder/" "" "5.182 ns" { ain h_adder:m1|r~14 } "NODE_NAME" } "" } } { "../h_adder/h_adder.vhd" "" { Text "E:/JACK/VHDL/h_adder/h_adder.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(2.108 ns) 10.009 ns rout 3 PIN PIN_183 0 " "Info: 3: + IC(1.250 ns) + CELL(2.108 ns) = 10.009 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'rout'" {  } { { "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" Compiler "f_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/f_adder/db/f_adder.quartus_db" { Floorplan "E:/JACK/VHDL/f_adder/" "" "3.358 ns" { h_adder:m1|r~14 rout } "NODE_NAME" } "" } } { "f_adder.vhd" "" { Text "E:/JACK/VHDL/f_adder/f_adder.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.167 ns 41.63 % " "Info: Total cell delay = 4.167 ns ( 41.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.842 ns 58.37 % " "Info: Total interconnect delay = 5.842 ns ( 58.37 % )" {  } {  } 0}  } { { "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" "" { Report "E:/JACK/VHDL/f_adder/db/f_adder_cmp.qrpt" Compiler "f_adder" "UNKNOWN" "V1" "E:/JACK/VHDL/f_adder/db/f_adder.quartus_db" { Floorplan "E:/JACK/VHDL/f_adder/" "" "10.009 ns" { ain h_adder:m1|r~14 rout } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.009 ns" { ain ain~out0 h_adder:m1|r~14 rout } { 0.000ns 0.000ns 4.592ns 1.250ns } { 0.000ns 1.469ns 0.590ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 22 15:56:56 2006 " "Info: Processing ended: Fri Sep 22 15:56:56 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}