📄 hex7.rpt
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
54 83 F OUTPUT t 0 0 0 0 4 0 0 hex0
57 88 F OUTPUT t 0 0 0 0 2 0 0 hex1
56 86 F OUTPUT t 0 0 0 0 2 0 0 hex2
55 85 F FF + t 0 0 0 0 5 4 2 hex3 (:6)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\myworks\taxi\hex7.rpt
hex7
** BURIED LOGIC **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 87 F SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1
- 84 F SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3
- 89 F TFFE + t 0 0 0 0 2 3 2 cnt2 (:7)
- 81 F DFFE + t 0 0 0 0 5 3 4 cnt1 (:8)
- 82 F TFFE + t 0 0 0 0 0 2 4 cnt0 (:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\myworks\taxi\hex7.rpt
hex7
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+----------------- LC83 hex0
| +--------------- LC88 hex1
| | +------------- LC86 hex2
| | | +----------- LC85 hex3
| | | | +--------- LC87 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1
| | | | | +------- LC84 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3
| | | | | | +----- LC89 cnt2
| | | | | | | +--- LC81 cnt1
| | | | | | | | +- LC82 cnt0
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC85 -> * * * * - * - * - | - - - - - * - - | <-- hex3
LC87 -> - - - - - - - * - | - - - - - * - - | <-- |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1
LC84 -> - - - * - - - - - | - - - - - * - - | <-- |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3
LC89 -> * - * * - * * * - | - - - - - * - - | <-- cnt2
LC81 -> * * - * * * * * - | - - - - - * - - | <-- cnt1
LC82 -> * - - * * * * * * | - - - - - * - - | <-- cnt0
Pin
83 -> - - - - - - - - - | - - - - - - - - | <-- clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\myworks\taxi\hex7.rpt
hex7
** EQUATIONS **
clk : INPUT;
-- Node name is ':9' = 'cnt0'
-- Equation name is 'cnt0', location is LC082, type is buried.
cnt0 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':8' = 'cnt1'
-- Equation name is 'cnt1', location is LC081, type is buried.
cnt1 = DFFE( _EQ001 $ _LC087, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = cnt0 & !cnt1 & !cnt2 & hex3 & _LC087;
-- Node name is ':7' = 'cnt2'
-- Equation name is 'cnt2', location is LC089, type is buried.
cnt2 = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = cnt0 & cnt1;
-- Node name is 'hex0'
-- Equation name is 'hex0', location is LC083, type is output.
hex0 = LCELL( _EQ003 $ VCC);
_EQ003 = !cnt0 & !cnt1 & !cnt2 & hex3
# !cnt0 & !hex3;
-- Node name is 'hex1'
-- Equation name is 'hex1', location is LC088, type is output.
hex1 = LCELL( _EQ004 $ cnt1);
_EQ004 = cnt1 & hex3;
-- Node name is 'hex2'
-- Equation name is 'hex2', location is LC086, type is output.
hex2 = LCELL( _EQ005 $ GND);
_EQ005 = cnt2 & !hex3;
-- Node name is 'hex3' = 'cnt3'
-- Equation name is 'hex3', location is LC085, type is output.
hex3 = DFFE( _EQ006 $ _LC084, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = cnt0 & !cnt1 & !cnt2 & hex3 & _LC084;
-- Node name is '|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC087', type is buried
_LC087 = LCELL( cnt1 $ cnt0);
-- Node name is '|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC084', type is buried
_LC084 = LCELL( hex3 $ _EQ007);
_EQ007 = cnt0 & cnt1 & cnt2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\myworks\taxi\hex7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,806K
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