📄 taxi.rpt
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Device-Specific Information: e:\myworks\taxi\taxi.rpt
taxi
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 8/ 8(100%) 0/16( 0%) 27/36( 75%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 3/16( 18%) 26/36( 72%)
C: LC33 - LC48 16/16(100%) 5/ 8( 62%) 11/16( 68%) 17/36( 47%)
D: LC49 - LC64 16/16(100%) 6/ 8( 75%) 9/16( 56%) 26/36( 72%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 16/16(100%) 1/ 8( 12%) 0/16( 0%) 21/36( 58%)
G: LC97 - LC112 16/16(100%) 1/ 8( 12%) 4/16( 25%) 18/36( 50%)
H: LC113 - LC128 4/16( 25%) 4/ 8( 50%) 1/16( 6%) 6/36( 16%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 33/64 ( 51%)
Total logic cells used: 100/128 ( 78%)
Total shareable expanders used: 21/128 ( 16%)
Total Turbo logic cells used: 100/128 ( 78%)
Total shareable expanders not available (n/a): 7/128 ( 5%)
Average fan-in: 6.85
Total fan-in: 685
Total input pins required: 4
Total fast input logic cells required: 0
Total output pins required: 26
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 100
Total flipflops required: 71
Total product terms required: 296
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 19
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\myworks\taxi\taxi.rpt
taxi
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 5 clk
5 (14) (A) INPUT 0 0 0 0 0 0 14 pulse
4 (16) (A) INPUT 0 0 0 0 0 5 55 start
6 (13) (A) INPUT 0 0 0 0 0 3 9 sw
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\myworks\taxi\taxi.rpt
taxi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
81 128 H OUTPUT t 0 0 0 0 3 0 0 char10
80 126 H OUTPUT t 0 0 0 0 2 0 0 char11
79 125 H OUTPUT t 0 0 0 0 2 0 0 char12
77 123 H FF t 1 1 0 1 5 5 5 char13 (:49)
28 40 C OUTPUT t 0 0 0 0 4 0 0 char20
29 38 C OUTPUT t 0 0 0 0 2 0 0 char21
30 37 C OUTPUT t 0 0 0 0 2 0 0 char22
31 35 C FF t 6 2 0 1 9 5 5 char23 (:53)
33 64 D OUTPUT t 0 0 0 0 4 0 0 char30
34 61 D OUTPUT t 0 0 0 0 2 0 0 char31
35 59 D OUTPUT t 0 0 0 0 2 0 0 char32
36 57 D FF t 1 1 0 1 9 3 0 char33 (:57)
39 53 D OUTPUT t 0 0 0 1 0 0 0 led
8 11 A OUTPUT t 0 0 0 0 4 0 0 out10
9 8 A OUTPUT t 0 0 0 0 2 0 0 out11
10 6 A OUTPUT t 0 0 0 0 2 0 0 out12
11 5 A FF + t 0 0 0 1 2 3 0 out13 (:79)
12 3 A OUTPUT t 0 0 0 0 4 0 0 out20
15 29 B OUTPUT t 0 0 0 0 2 0 0 out21
16 27 B OUTPUT t 0 0 0 0 2 0 0 out22
17 25 B FF + t 0 0 0 1 2 3 0 out23 (:83)
18 24 B OUTPUT t 0 0 0 0 4 0 0 out30
20 21 B OUTPUT t 0 0 0 0 2 0 0 out31
21 19 B OUTPUT t 0 0 0 0 2 0 0 out32
22 17 B FF + t 0 0 0 1 2 3 0 out33 (:87)
37 56 D FF + t 0 0 0 1 4 0 21 waits (:66)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\myworks\taxi\taxi.rpt
taxi
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 95 F SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:159|addcore:adder|result_node2
(61) 94 F SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:159|addcore:adder|result_node3
- 90 F SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:159|addcore:adder|result_node4
(56) 86 F SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:159|addcore:adder|result_node5
(58) 91 F SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:159|addcore:adder|result_node6
(25) 45 C SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:620|addcore:adder|addcore:adder0|result_node1
(24) 46 C SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:620|addcore:adder|addcore:adder0|result_node3
- 103 G SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:2177|addcore:adder|addcore:adder0|result_node5
- 106 G SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:2177|addcore:adder|addcore:adder0|result_node6
(67) 104 G SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:2177|addcore:adder|addcore:adder0|result_node7
- 89 F DFFE t 0 0 0 2 7 0 12 pulse2 (:31)
- 18 B DFFE t 1 0 0 2 11 3 8 temp2 (:32)
- 42 C DFFE t 0 0 0 1 6 1 12 k13 (:33)
- 44 C TFFE t 0 0 0 1 3 0 13 k12 (:34)
- 36 C DFFE t 0 0 0 1 6 0 15 k11 (:35)
(27) 43 C TFFE t 0 0 0 1 1 0 15 k10 (:36)
(14) 32 B TFFE t 0 0 0 1 9 1 7 k23 (:38)
- 22 B TFFE t 0 0 0 1 7 0 8 k22 (:39)
- 23 B TFFE t 1 0 1 1 9 0 9 k21 (:40)
- 47 C TFFE t 0 0 0 1 5 0 8 k20 (:41)
- 31 B TFFE t 0 0 0 1 13 1 3 k33 (:42)
- 26 B TFFE t 0 0 0 1 11 0 4 k32 (:43)
- 28 B TFFE t 1 0 1 1 13 0 5 k31 (:44)
- 20 B TFFE t 0 0 0 1 9 0 5 k30 (:45)
(65) 101 G DFFE + t 0 0 0 1 10 3 9 mc (:47)
- 41 C DFFE t 1 1 0 1 5 4 5 c12 (:50)
- 33 C DFFE t 1 1 0 1 5 4 5 c11 (:51)
- 39 C TFFE t 2 1 1 1 7 4 5 c22 (:54)
- 58 D DFFE t 8 1 1 1 9 4 6 c21 (:55)
(23) 48 C TFFE t 6 2 0 1 9 3 6 c20 (:56)
- 63 D TFFE t 1 1 0 1 8 3 0 c32 (:58)
- 62 D TFFE t 1 1 0 1 7 3 1 c31 (:59)
- 34 C TFFE t 1 1 0 1 6 2 2 c30 (:60)
- 55 D TFFE t 1 1 0 3 4 1 0 jsq4 (:61)
- 60 D TFFE t 1 1 0 3 3 1 1 jsq3 (:62)
- 54 D TFFE t 1 1 0 3 2 1 2 jsq2 (:63)
- 52 D TFFE t 1 1 0 3 1 1 3 jsq1 (:64)
(40) 51 D TFFE t 1 1 0 3 0 0 4 jsq0 (:65)
- 1 A TFFE + t 0 0 0 1 5 1 10 se13 (:67)
- 108 G TFFE + t 0 0 0 1 3 0 11 se12 (:68)
(70) 109 G TFFE + t 0 0 0 1 5 0 12 se11 (:69)
(63) 97 G TFFE + t 0 0 0 1 1 0 12 se10 (:70)
- 12 A TFFE + t 0 0 0 1 8 1 6 se23 (:71)
(5) 14 A TFFE + t 0 0 0 1 9 0 8 se22 (:72)
(4) 16 A TFFE + t 0 0 0 1 9 0 8 se21 (:73)
- 98 G TFFE + t 0 0 0 1 5 0 8 se20 (:74)
- 4 A TFFE + t 0 0 0 1 13 1 2 mi13 (:75)
- 9 A TFFE + t 0 0 0 1 11 0 3 mi12 (:76)
- 7 A TFFE + t 0 0 0 1 13 0 4 mi11 (:77)
- 10 A TFFE + t 0 0 0 1 9 0 4 mi10 (:78)
- 50 D DFFE + t 0 0 0 1 2 2 0 o12 (:80)
(41) 49 D DFFE + t 0 0 0 1 2 2 0 o11 (:81)
- 15 A DFFE + t 0 0 0 1 2 1 0 o10 (:82)
(6) 13 A DFFE + t 0 0 0 1 2 2 0 o22 (:84)
- 2 A DFFE + t 0 0 0 1 2 2 0 o21 (:85)
- 30 B DFFE + t 0 0 0 1 2 1 0 o20 (:86)
- 87 F DFFE + t 0 0 0 1 2 2 0 o32 (:88)
(55) 85 F DFFE + t 0 0 0 1 2 2 0 o31 (:89)
- 84 F DFFE + t 0 0 0 1 2 1 0 o30 (:90)
(54) 83 F DFFE t 0 0 0 2 8 0 7 fp6 (:93)
- 82 F DFFE t 0 0 0 2 8 0 8 fp5 (:94)
- 81 F DFFE t 0 0 0 2 8 0 9 fp4 (:95)
(62) 96 F DFFE t 0 0 0 2 8 0 10 fp3 (:96)
(60) 93 F DFFE t 0 0 0 2 8 0 11 fp2 (:97)
- 92 F TFFE t 0 0 0 2 1 0 11 fp1 (:98)
(57) 88 F TFFE t 0 0 0 2 0 0 12 fp0 (:99)
- 102 G DFFE + t 1 0 1 1 10 0 9 wjsq7 (:1735)
(68) 105 G DFFE + t 1 0 1 1 10 0 10 wjsq6 (:1736)
- 100 G DFFE + t 1 0 1 1 10 0 11 wjsq5 (:1737)
(64) 99 G TFFE + t 0 0 0 1 9 0 11 wjsq4 (:1738)
(71) 112 G TFFE + t 1 0 0 1 9 0 11 wjsq3 (:1739)
- 111 G TFFE + t 0 0 0 1 9 0 11 wjsq2 (:1740)
- 110 G TFFE + t 0 0 0 1 9 0 11 wjsq1 (:1741)
(69) 107 G TFFE + t 0 0 0 1 1 0 11 wjsq0 (:1742)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\myworks\taxi\taxi.rpt
taxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC11 out10
| +----------------------------- LC8 out11
| | +--------------------------- LC6 out12
| | | +------------------------- LC5 out13
| | | | +----------------------- LC3 out20
| | | | | +--------------------- LC1 se13
| | | | | | +------------------- LC12 se23
| | | | | | | +----------------- LC14 se22
| | | | | | | | +--------------- LC16 se21
| | | | | | | | | +------------- LC4 mi13
| | | | | | | | | | +----------- LC9 mi12
| | | | | | | | | | | +--------- LC7 mi11
| | | | | | | | | | | | +------- LC10 mi10
| | | | | | | | | | | | | +----- LC15 o10
| | | | | | | | | | | | | | +--- LC13 o22
| | | | | | | | | | | | | | | +- LC2 o21
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC5 -> * * * - - - - - - - - - - - - - | * - - - - - - - | <-- out13
LC1 -> - - - * - * * * * * * * * - - - | * - - - - - * - | <-- se13
LC12 -> - - - - - - * * * * * * * - - - | * * - - - - - - | <-- se23
LC14 -> - - - - - - * * * * * * * - * - | * - - - - - - - | <-- se22
LC16 -> - - - - - - * * * * * * * - - * | * - - - - - - - | <-- se21
LC4 -> - - - - - - - - - * - * - - - - | * * - - - - - - | <-- mi13
LC9 -> - - - - - - - - - * * * - - - - | * - - - - * - - | <-- mi12
LC7 -> - - - - - - - - - * * * - - - - | * - - - - * - - | <-- mi11
LC10 -> - - - - - - - - - * * * * - - - | * - - - - * - - | <-- mi10
LC15 -> * - - - - - - - - - - - - - - - | * - - - - - - - | <-- o10
LC13 -> - - - - * - - - - - - - - - - - | * * - - - - - - | <-- o22
LC2 -> - - - - * - - - - - - - - - - - | * * - - - - - - | <-- o21
Pin
83 -> - - - - - - - - - - - - - - - - | - - - * - - - - | <-- clk
4 -> - - - - - * * * * * * * * - - - | * * * * - * * * | <-- start
6 -> - - - * - - - - - - - - - * * * | * * - * - * - - | <-- sw
LC25 -> - - - - * - - - - - - - - - - - | * * - - - - - - | <-- out23
LC56 -> - - - - - * * * * * * * * - - - | * - - - - - * - | <-- waits
LC42 -> - - - * - - - - - - - - - - - - | * * * - - - - - | <-- k13
LC43 -> - - - - - - - - - - - - - * - - | * * * - - - - - | <-- k10
LC22 -> - - - - - - - - - - - - - - * - | * * - - - - - - | <-- k22
LC23 -> - - - - - - - - - - - - - - - * | * * - - - - - - | <-- k21
LC108-> - - - - - * * * * * * * * - - - | * - - * - - * - | <-- se12
LC109-> - - - - - * * * * * * * * - - - | * - - * - - * - | <-- se11
LC97 -> - - - - - * * * * * * * * * - - | * - - - - - * - | <-- se10
LC98 -> - - - - - - * * * * * * * - - - | * * - - - - - - | <-- se20
LC50 -> * - * - - - - - - - - - - - - - | * - - - - - - - | <-- o12
LC49 -> * * - - - - - - - - - - - - - - | * - - - - - - - | <-- o11
LC30 -> - - - - * - - - - - - - - - - - | * - - - - - - - | <-- o20
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
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