📄 taxi.rpt
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Project Information e:\myworks\taxi\taxi.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 09/27/2006 16:44:59
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
TAXI
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
taxi EPM7128SLC84-15 4 26 0 100 21 78 %
User Pins: 4 26 0
Project Information e:\myworks\taxi\taxi.rpt
** PROJECT COMPILATION MESSAGES **
Warning: GLOBAL primitive on node 'clk' feeds logic -- non-global signal usage may result
Warning: Flipflop ':52' stuck at GND
Project Information e:\myworks\taxi\taxi.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\myworks\taxi\taxi.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
taxi@81 char10
taxi@80 char11
taxi@79 char12
taxi@77 char13
taxi@28 char20
taxi@29 char21
taxi@30 char22
taxi@31 char23
taxi@33 char30
taxi@34 char31
taxi@35 char32
taxi@36 char33
taxi@83 clk
taxi@39 led
taxi@8 out10
taxi@9 out11
taxi@10 out12
taxi@11 out13
taxi@12 out20
taxi@15 out21
taxi@16 out22
taxi@17 out23
taxi@18 out30
taxi@20 out31
taxi@21 out32
taxi@22 out33
taxi@5 pulse
taxi@4 start
taxi@6 sw
taxi@37 waits
Project Information e:\myworks\taxi\taxi.rpt
** FILE HIERARCHY **
|lpm_add_sub:159|
|lpm_add_sub:159|addcore:adder|
|lpm_add_sub:159|altshift:result_ext_latency_ffs|
|lpm_add_sub:159|altshift:carry_ext_latency_ffs|
|lpm_add_sub:159|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:399|
|lpm_add_sub:399|addcore:adder|
|lpm_add_sub:399|addcore:adder|addcore:adder0|
|lpm_add_sub:399|altshift:result_ext_latency_ffs|
|lpm_add_sub:399|altshift:carry_ext_latency_ffs|
|lpm_add_sub:399|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:443|
|lpm_add_sub:443|addcore:adder|
|lpm_add_sub:443|addcore:adder|addcore:adder0|
|lpm_add_sub:443|altshift:result_ext_latency_ffs|
|lpm_add_sub:443|altshift:carry_ext_latency_ffs|
|lpm_add_sub:443|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:486|
|lpm_add_sub:486|addcore:adder|
|lpm_add_sub:486|addcore:adder|addcore:adder0|
|lpm_add_sub:486|altshift:result_ext_latency_ffs|
|lpm_add_sub:486|altshift:carry_ext_latency_ffs|
|lpm_add_sub:486|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:620|
|lpm_add_sub:620|addcore:adder|
|lpm_add_sub:620|addcore:adder|addcore:adder0|
|lpm_add_sub:620|altshift:result_ext_latency_ffs|
|lpm_add_sub:620|altshift:carry_ext_latency_ffs|
|lpm_add_sub:620|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1002|
|lpm_add_sub:1002|addcore:adder|
|lpm_add_sub:1002|addcore:adder|addcore:adder0|
|lpm_add_sub:1002|altshift:result_ext_latency_ffs|
|lpm_add_sub:1002|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1002|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1040|
|lpm_add_sub:1040|addcore:adder|
|lpm_add_sub:1040|addcore:adder|addcore:adder0|
|lpm_add_sub:1040|altshift:result_ext_latency_ffs|
|lpm_add_sub:1040|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1040|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1078|
|lpm_add_sub:1078|addcore:adder|
|lpm_add_sub:1078|addcore:adder|addcore:adder0|
|lpm_add_sub:1078|altshift:result_ext_latency_ffs|
|lpm_add_sub:1078|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1078|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1116|
|lpm_add_sub:1116|addcore:adder|
|lpm_add_sub:1116|addcore:adder|addcore:adder0|
|lpm_add_sub:1116|altshift:result_ext_latency_ffs|
|lpm_add_sub:1116|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1116|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1360|
|lpm_add_sub:1360|addcore:adder|
|lpm_add_sub:1360|addcore:adder|addcore:adder0|
|lpm_add_sub:1360|altshift:result_ext_latency_ffs|
|lpm_add_sub:1360|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1360|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1560|
|lpm_add_sub:1560|addcore:adder|
|lpm_add_sub:1560|addcore:adder|addcore:adder0|
|lpm_add_sub:1560|altshift:result_ext_latency_ffs|
|lpm_add_sub:1560|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1560|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1867|
|lpm_add_sub:1867|addcore:adder|
|lpm_add_sub:1867|addcore:adder|addcore:adder0|
|lpm_add_sub:1867|altshift:result_ext_latency_ffs|
|lpm_add_sub:1867|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1867|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1911|
|lpm_add_sub:1911|addcore:adder|
|lpm_add_sub:1911|addcore:adder|addcore:adder0|
|lpm_add_sub:1911|altshift:result_ext_latency_ffs|
|lpm_add_sub:1911|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1911|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2058|
|lpm_add_sub:2058|addcore:adder|
|lpm_add_sub:2058|addcore:adder|addcore:adder0|
|lpm_add_sub:2058|altshift:result_ext_latency_ffs|
|lpm_add_sub:2058|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2058|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2177|
|lpm_add_sub:2177|addcore:adder|
|lpm_add_sub:2177|addcore:adder|addcore:adder1|
|lpm_add_sub:2177|addcore:adder|addcore:adder0|
|lpm_add_sub:2177|altshift:result_ext_latency_ffs|
|lpm_add_sub:2177|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2177|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\myworks\taxi\taxi.rpt
taxi
***** Logic for device 'taxi' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R
E E
V c c c c S S
o o o o p s C h h h V h E E
u u u u u t C a a a C a R R
t t t t G l a I G G G c G r r r C r V V
1 1 1 1 N s s r N N N N l N 1 1 1 I 1 E E
3 2 1 0 D w e t T D D D k D 0 1 2 O 3 D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
out20 | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
out21 | 15 71 | #TDO
out22 | 16 70 | RESERVED
out23 | 17 69 | RESERVED
out30 | 18 68 | RESERVED
GND | 19 67 | RESERVED
out31 | 20 66 | VCCIO
out32 | 21 65 | RESERVED
out33 | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
char20 | 28 58 | RESERVED
char21 | 29 57 | RESERVED
char22 | 30 56 | RESERVED
char23 | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
c c c c w V l R R G V R R R G R R R R R V
h h h h a C e E E N C E E E N E E E E E C
a a a a i C d S S D C S S S D S S S S S C
r r r r t I E E I E E E E E E E E I
3 3 3 3 s O R R N R R R R R R R R O
0 1 2 3 V V T V V V V V V V V
E E E E E E E E E E
D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
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