hd_pass_ics664.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

--
-- Error capture flip-flop
--
-- This flip-flop get set when CRC errors are detected and is reset with
-- push button 3.
--
process(rx_usrclk)
begin
    if rx_usrclk'event and rx_usrclk='1' then
        if clr_errs = '1' then
            crc_err_ff <= '0';
        elsif rx_locked = '1' then
            if rx_c_crc_err = '1' or rx_y_crc_err = '1' then
                crc_err_ff <= '1';
            end if;
        end if;
    end if;
end process;

--
-- hdsdi_tx_path
--
-- This module contains the line number insertion logic, CRC generation and
-- insertion logic, and the HD-SDI encoder.
--
insert_ln <= rx_new_ln_valid and insert_new_ln;

TXPATH1 : hdsdi_tx_path 
    port map (
        clk             => rx_usrclk,
        rst             => '0',
        ce              => '1',
        c_in            => rx_vid_c,
        y_in            => rx_vid_y,
        nrzi            => '1',
        scram           => '1',
        insert_crc      => insert_new_crc,  -- DIP switch controls CRC insertion/pass through
        force_crc_err   => '0',
        insert_ln       => insert_ln,       -- DIP switch controls LN insertion/pass through
        ln              => rx_new_ln,
        eav             => rx_eav,
        sav             => rx_sav,
        q               => tx_data);

-------------------------------------------------------------------------------
-- Standalone transmitter section
--
-- This transmitter drives the MR-Tx2 output connector with HD-SDI video
-- generated by an internal video pattern generator.
--

--
-- Input registers for the video standard select inputs (dipsw[7:5])
--
-- The video format generated by the multigenHD video pattern generator is
-- determined by three DIP switches. The registers below synchronize these
-- inputs to the txusrclk.
--
process(tx2_usrclk)
begin
    if tx2_usrclk'event and tx2_usrclk='1' then
        stdsel_reg <= dipsw(7 downto 5);
    end if;
end process;

process(tx2_usrclk)
begin
    if tx2_usrclk'event and tx2_usrclk='1' then
        stdsel_syncreg <= stdsel_reg;
    end if;
end process;

--
-- Video generator
--
-- This pattern generator can produce eight different video formats that are
-- HD-SDI compatible.
--
tx2_patsel(0) <= dipsw(2) and dipsw(1);
tx2_patsel(1) <= dipsw(2);
tx2_insert_logo <= not dipsw(2) and not dipsw(1);

VIDGEN : multigenHD_logo
    port map (
        clk            => tx2_usrclk,
        rst            => '0',
        ce             => '1',
        std            => stdsel_syncreg,
        pattern        => tx2_patsel,
        user_opt       => "00",
        insert_logo    => tx2_insert_logo,
        y              => tx2_vid_y,
        c              => tx2_vid_c,
        h_blank        => open,
        v_blank        => open,
        field          => open,
        trs            => open,
        xyz            => tx2_xyz,
        line_num       => tx2_ln);
    
tx2_sav <= not tx2_vid_y(6) and tx2_xyz;
tx2_eav <= tx2_vid_y(6) and tx2_xyz;

--
-- HD-SDI transmitter
--
-- This module does line number generation and insertion, CRC generation and
-- insertion, and HD-SDI encoding.
--
TXPATH2 : hdsdi_tx_path 
    port map (
        clk            => tx2_usrclk,
        rst            => '0',
        ce             => '1',
        c_in           => tx2_vid_c,
        y_in           => tx2_vid_y,
        nrzi           => '1',
        scram          => '1',
        insert_crc     => '1',
        force_crc_err  => tx2_force_crc_err,
        insert_ln      => '1',
        ln             => tx2_ln,
        eav            => tx2_eav,
        sav            => tx2_sav,
        q              => tx2_data);
                      
--
-- RocketIO Transceiver
--
-- This is the RocketIO transceiver. Inside this module are bit-swappers 
-- needed to match the bit order of HD-SDI (LSB first) to the bit order of
-- the RocketIO module (MSB first). 
--
RIO2 : hdsdi_rio 
    port map (
        brefclk        => clk_74_17M,
        brefclk2       => clk_74_25M,
        refclk         => '0',
        refclk2        => '0',
        refclk_sel     => tx2_refclksel,
        rst            => '0',
        loopback_en    => '0',
        loopback_mode  => '0',
        txinhibit      => '0',
        txdata         => tx2_data,
        txusrclk       => tx2_usrclk,
        txusrclk2      => tx2_usrclk,
        rxusrclk       => tx2_usrclk,
        rxusrclk2      => tx2_usrclk,
        dcm_locked     => '1',
        rxp            => mr_rx2_rxp,
        rxn            => mr_rx2_rxn,
        rxdata         => open,
        rxrecclk       => open,
        txp            => mr_tx2_txp,
        txn            => mr_tx2_txn);

-------------------------------------------------------------------------------
-- Test signal outputs to board header
--
rx_crc_err <= rx_y_crc_err or rx_c_crc_err;

TP0 : OBUF_LVCMOS25 
    port map (
        I   => rx_usrclk,
        O   => test_point(0));

TP1 : OBUF_LVCMOS25 
    port map (
        I   => rx_crc_err,
        O   => test_point(1));

TP2 : OBUF_LVCMOS25 
    port map (
        I   => rx_field,
        O   => test_point(2));

TP3 : OBUF_LVCMOS25 
    port map (
        I   => rx_v_blank,
        O   => test_point(3));

TP4 : OBUF_LVCMOS25 
    port map (
        I   => rx_h_blank,
        O   => test_point(4));

TP5 : OBUF_LVCMOS25 
    port map (
        I   => '0',
        O   => test_point(5));

TP6 : OBUF_LVCMOS25 
    port map (
        I   => '0',
        O   => test_point(6));

TP7 : OBUF_LVCMOS25 
    port map (
        I   => '0',
        O   => test_point(7));

TP8 : OBUF_LVCMOS25 
    port map (
        I   => '0',
        O   => test_point(8));

TP9 : OBUF_LVCMOS25 
    port map (
        I   => '0',
        O   => test_point(9));

-------------------------------------------------------------------------------
-- Output buffers required to drive SDV board components that are not used by
-- this demo.
--

-- HD-SDI VCXO
HDVCXO_U : OBUF_LVCMOS33
    port map (
        I => '0',
        O => hd_vcxo_up);

HDVCXO_D : OBUF_LVCMOS33
    port map (
        I => '0',
        O => hd_vcxo_down);

-- SDI 270MHz VCO

SDVCO_U : OBUF_LVCMOS33 
    port map (
        I => '0', 
        O => sdi_vco_up);

SDVCO_D : OBUF_LVCMOS33 
    port map (
        I => '0', 
        O => sdi_vco_down);

-- CY22394 PLL

CYP_OE : OBUF_LVCMOS33 
    port map (
        I => '0',
        O => cypll_oe);

CYP_S2 : OBUF_LVCMOS33 
    port map (
        I => '0', 
        O => cypll_s2);

CYP_SC : OBUF_LVCMOS33 
    port map (
        I => '0', 
        O => cypll_sclk);

CYP_SD: OBUF_LVCMOS33 
    port map (
        I => '0', 
        O => cypll_sdat);

-- ICS8745 PLL

I8745_COUT : OBUFDS_LVDS_25 
    port map (
        I  => '0', 
        O  => ics8745_clkout_p, 
        OB => ics8745_clkout_n);

I8745_SEL0 : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => ics8745_sel(0));

I8745_SEL1 : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => ics8745_sel(1));

I8745_SEL2 : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => ics8745_sel(2));

I8745_SEL3 : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => ics8745_sel(3));

I8745_PLLSEL : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => ics8745_pll_sel);

I8745_MR : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => ics8745_mr);

-- SDI-Tx Port

SDI_TXD : OBUFDS_LVDS_25 
    port map (
        I  => '0', 
        O  => sdi_tx_dout_p, 
        OB => sdi_tx_dout_n);

-- ASI-Tx Port
ASI_TXD : OBUFDS_LVDS_25 
    port map (
        I  => '0', 
        O  => asi_tx_p, 
        OB => asi_tx_n);

-- RS-232 Port

RX232TXD : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => rs232_txd);

RS232RTS : OBUF_LVCMOS25 
    port map (
        I => '0', 
        O => rs232_rts);

end synth;