📄 hd_pass_ics664.vhd
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O => mr_rate_led);
LED9 : OBUF_LVCMOS25
port map (
I => sdi_sync_led_out,
O => sdi_sync_led);
LED10 : OBUF_LVCMOS25
port map (
I => sdi_rate_led_out,
O => sdi_rate_led);
LED11 : OBUF_LVCMOS25
port map (
I => mode_mr_led_out,
O => mode_mr_led);
LED12 : OBUF_LVCMOS25
port map (
I => mode_sdi_led_out,
O => mode_sdi_led);
LED13 : OBUF_LVCMOS25
port map (
I => mode_asi_led_out,
O => mode_asi_led);
--
-- GS1528 Cable Driver slew rate control output
--
-- The GS1528 cable driver has a slew rate control input that tells it whether
-- to compliant with SDI or HD-SDI slew rates. In this demo, we are always
-- transmitting HD-SDI, so we always force this signal low.
--
MRTX2_SLEW : OBUF_LVCMOS33
port map (
I => '0',
O => mr_tx2_slewrate);
MRTX1_SLEW : OBUF_LVCMOS33
port map (
I => '0',
O => mr_tx1_slewrate);
--
-- 74.25M XO input buffer
--
HDXO1 : IBUFGDS
port map (
O => clk_74_25M,
I => clk_74_25M_p,
IB => clk_74_25M_n);
--
-- 74.1758MHz XO input buffer
--
HDXOM : IBUFGDS
port map (
O => clk_74_17M,
I => clk_74_17M_p,
IB => clk_74_17M_n);
--
-- BUFGMUX to generate tx_usrclk
--
BFG1 : BUFGMUX
port map (
I0 => clk_74_17M,
I1 => clk_74_25M,
S => tx2_refclksel,
O => tx2_usrclk);
--
-- HD-SDI VCXO input buffer
--
I664_IN : IBUF_LVDCI_25
port map (
O => clk_ics664,
I => ics664_in);
I664_S0 : OBUF_LVCMOS33
port map (
I => not rate_sel,
O => ics664_s(0));
I664_S1 : OBUF_LVCMOS33
port map (
I => '1',
O => ics664_s(1));
I664_S2 : OBUF_LVCMOS33
port map (
I => '0',
O => ics664_s(2));
I664_S3 : OBUF_LVCMOS33
port map (
I => '0',
O => ics664_s(3));
-- SDI 27MHz VCXO
SDVCXO_U : OBUF_LVCMOS33
port map (
I => make_vcxo_faster,
O => vcxo_27M_up);
SDVCXO_D : OBUF_LVCMOS33
port map (
I => make_vcxo_slower,
O => vcxo_27M_down);
VCXO27M_LPFEN : OBUF_LVCMOS33
port map (
O => vcxo_27M_sel,
I => '0'); -- enable loop filter
--
-- 33MHz clock input buffer
--
XO33 : IBUF_LVCMOS25
port map (
O => clk_33M,
I => clk_33M_in);
BUFG33M : BUFG
port map (
O => gclk_33M,
I => clk_33M);
ACECLKEN : OBUF_LVCMOS25
port map (
O => ace_clk_en,
I => '0');
--
-- LED control block
--
--
-- LED control block
--
LEDC : led_control
port map (
clk => gclk_33M,
mr_tx2_on => '1',
mr_tx2_fast => '0',
mr_tx2_slow => '0',
mr_tx1_on => '1',
mr_tx1_fast => '0',
mr_tx1_slow => '0',
mr_rx_on => heartbeat,
mr_rx_fast => '0',
mr_rx_slow => '0',
asi_tx_on => '0',
asi_tx_fast => '0',
asi_tx_slow => '0',
sdi_rx_on => '0',
sdi_rx_fast => '0',
sdi_rx_slow => '0',
sdi_tx_on => '0',
sdi_tx_fast => '0',
sdi_tx_slow => '0',
mr_sync_on => rx_locked,
mr_sync_fast => '0',
mr_sync_slow => not rx_locked,
mr_hd_on => rate_sel,
mr_hd_fast => '0',
mr_hd_slow => '0',
mr_rate_on => rx_format(3),
mr_rate_fast => '0',
mr_rate_slow => '0',
sdi_sync_on => rx_format(2),
sdi_sync_fast => '0',
sdi_sync_slow => '0',
sdi_rate_on => rx_format(1),
sdi_rate_fast => '0',
sdi_rate_slow => '0',
mode_mr_on => rx_format(0),
mode_mr_fast => '0',
mode_mr_slow => '0',
mode_sdi_on => '0',
mode_sdi_fast => '0',
mode_sdi_slow => '0',
mode_asi_on => '0',
mode_asi_fast => crc_err_ff,
mode_asi_slow => '0',
mr_tx2_led => mr_tx2_led_out,
mr_tx1_led => mr_tx1_led_out,
mr_rx_led => mr_rx_led_out,
asi_tx_led => asi_tx_led_out,
sdi_rx_led => sdi_rx_led_out,
sdi_tx_led => sdi_tx_led_out,
mr_sync_led => mr_sync_led_out,
mr_hd_led => mr_hd_led_out,
mr_rate_led => mr_rate_led_out,
sdi_sync_led => sdi_sync_led_out,
sdi_rate_led => sdi_rate_led_out,
mode_mr_led => mode_mr_led_out,
mode_sdi_led => mode_sdi_led_out,
mode_asi_led => mode_asi_led_out
);
-------------------------------------------------------------------------------
-- HD-SDI Pass-through Section
--
--
-- RocketIO Transceiver
--
-- This is the RocketIO transceiver. Inside this module are bit-swappers
-- needed to match the bit order of HD-SDI (LSB first) to the bit order of
-- the Rocket IO module (MSB first).
--
RIO1 : hdsdi_rio_refclk
port map (
brefclk => '0',
brefclk2 => '0',
refclk => clk_ics664,
refclk2 => '0',
refclk_sel => '0',
rst => '0',
loopback_en => '0',
loopback_mode => '0',
txinhibit => '0',
txdata => tx_data,
txusrclk => rx_usrclk,
txusrclk2 => rx_usrclk,
rxusrclk => rx_usrclk,
rxusrclk2 => rx_usrclk,
dcm_locked => '1',
rxp => mr_rx_rxp,
rxn => mr_rx_rxn,
rxdata => rx_data,
rxrecclk => rx_recclk,
txp => mr_tx1_txp,
txn => mr_tx1_txn);
RXCLK_BUFG : BUFG
port map (
O => rx_usrclk,
I => rx_recclk);
--
-- Phase detector for HD VCXO PLL
--
-- This PLL locks the HD VCXO to the clock recovered by the RocketIO receiver
-- and produces a low jitter clock running at the same frequency as the
-- recovered clock.
--
phasedet : phasedetHD
port map (
vco => clk_ics664,
refclk => rx_recclk,
reset => '0',
mkvcofaster => make_vcxo_faster,
mkvcoslower => make_vcxo_slower,
vco_tc => open,
refclk_tc => open);
--
-- HD-SDI receiver
--
-- This module decscrambles and frames the data received by the RocketIO
-- receiver. The recovered data is checked for errors.
--
RX : hdsdi_rx2
port map (
clk => rx_usrclk,
ce => '1',
rst => '0',
dec_bypass => '0',
frame_en => rx_nsp,
rxdata => rx_data,
c_out => rx_vid_c,
y_out => rx_vid_y,
nsp => rx_nsp,
trs => open,
xyz => rx_xyz,
eav => rx_eav,
sav => rx_sav,
trs_err => rx_trs_err,
rx_ln => rx_ln,
gen_ln => rx_new_ln,
gen_ln_valid => rx_new_ln_valid,
c_crc_err => rx_c_crc_err,
y_crc_err => rx_y_crc_err,
std => rx_format,
std_locked => rx_locked);
--
-- Bit rate detection & control module
--
ARATE : hdsdi_rx_autorate
port map (
clk => rx_usrclk,
rst => '0',
sav => rx_sav,
trs_err => rx_trs_err,
y_crc_err => rx_y_crc_err,
c_crc_err => rx_c_crc_err,
refclksel => rate_sel);
--
-- This optional module generates some decoding video timing information.
--
TMG : hdsdi_rx_timing
port map (
clk => rx_usrclk,
rst => '0',
ln_in => rx_ln,
vid_in => rx_vid_y,
xyz => rx_xyz,
sav => rx_sav,
frame_start => open,
field => rx_field,
v_blank => rx_v_blank,
h_blank => rx_h_blank,
horz_position => open);
--
-- This module divides the TRS signal frequency down to a visible flash rate
-- to drive the Rx Heartbeat LED.
--
HBEAT : rx_heartbeat
port map (
clk => rx_usrclk,
xyz => rx_xyz,
trs_err => rx_trs_err,
heartbeat => heartbeat);
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