hdsdi_tx_path.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: hdsdi_tx_path.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 14:53:54-07 $
-- /___/   /\    Date Created: May 28, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: hdsdi_tx_path.vhd,rcs $
-- Revision 1.1  2004-12-09 14:53:54-07  jsnow
-- Cosmetic changes only.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
--
-- Description of module:
-- 
-- This contains most of the data path for the HD-SDI transmitter. It will 
-- insert line numbers into the video stream (the line numbers are generated 
-- external to this module). It will calculate the CRC values for each line and 
-- insert them into the Y and C channels. Finally, it encodes the video and 
-- produces 20 bits of encoded data ready for serialization.
-- 
-- There are several control inputs to this module:
-- 
-- insert_ln: a high enables the module to insert the line numbers from the ln
-- port into the video channels.
-- 
-- insert_crc: a high enables the module to insert the CRC values it calculates
-- into the video channels.
-- 
-- nrzi: a high enables the NRZ-to-NRZI portion of the SMPTE encoding algorithm
-- 
-- scram: a high enables the scrambling portion of the SMPTE encoding algorithm
-- 
-- force_crc_err: when high, this input forces the module to generate a bad CRC
-- value which will be inserted into only the C channel if insert_crc is also 
-- high. The Y channel CRC value will not be affected.
--  
-- The module also has the following timing and data inputs:
-- 
-- c_in, y_in: C and Y channel video inputs
-- 
-- ln: line number input port
-- 
-- eav: must be asserted when the XYZ word of an EAV is present on c_in and y_in
-- 
-- sav: must be asserted when the XYZ word of an SAV is present on c_in and y_in
-- 
-- The module does not contain any input or output registers. If timing can not 
-- be met on the input side of the module, place pipeline delay registers on the
-- c_in, y_in, eav, and sav signals. The ln port may not need a pipeline delay
-- register if it remains asserted for several clock cycles after the EAV.
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;

entity hdsdi_tx_path is
    port (
        clk:            in  std_logic;      -- clock input
        rst:            in  std_logic;      -- async reset input
        ce:             in  std_logic;      -- clock enable input
        c_in:           in  hd_video_type;  -- chroma channel data input
        y_in:           in  hd_video_type;  -- luma channel data input
        nrzi:           in  std_logic;      -- high enables NRZ-to-NRZ conversino
        scram:          in  std_logic;      -- high enables SMPTE 292M scrambler
        insert_crc:     in  std_logic;      -- high enables generation & insertion of CRCs
        force_crc_err:  in  std_logic;      -- high forces CRC error to be generated
        insert_ln:      in  std_logic;      -- high enables line number insertion
        ln:             in  hd_vpos_type;   -- line numbers to be inserted
        eav:            in  std_logic;      -- input asserted during XYZ word of EAV symbol
        sav:            in  std_logic;      -- input asserted during XYZ word of SAV symbol
        q:              out hd_vid20_type   -- encoded data output
    );
end hdsdi_tx_path;

architecture synth of hdsdi_tx_path is

--
-- Internal signals
--
signal c_crc_calc :     hd_crc18_type;               -- output of C channel CRC generator
signal c_crc_out :      hd_crc18_type;               -- CRC with forced CRC errors if force_crc_err asserted
signal y_crc_out :      hd_crc18_type;               -- output of Y channel CRC generator
signal c_ln_out :       hd_video_type;               -- output of C channel line number inserter
signal y_ln_out :       hd_video_type;               -- output of Y channel line number inserter
signal c_crc_ins_out :  hd_video_type;               -- C channel after CRC insertion
signal y_crc_ins_out :  hd_video_type;               -- Y channel after CRC insertion
signal crc_en :         std_logic;                   -- controls which words are included in CRC calculations
signal clr_crc :        std_logic;                   -- clears the CRC calculators to start new calculation
signal eav_dly :        std_logic_vector(3 downto 0);-- shift reg used to create video timing
signal crc_en_ce :      std_logic;                   -- crc_en AND crc

component hdsdi_insert_ln
    port (
        insert_ln:  in  std_logic;      -- enables insertion of line numbers when 1
        ln_word0:   in  std_logic;      -- input asserted during time for first LN word in EAV
        ln_word1:   in  std_logic;      -- input asserted during time for second LN word in EAV
        c_in:       in  hd_video_type;  -- C channel video input
        y_in:       in  hd_video_type;  -- Y channel video input
        ln:         in  hd_vpos_type;   -- line number inputs
        c_out:      out hd_video_type;  -- C channel video output
        y_out:      out hd_video_type   -- Y channel video output
    );
end component;

component hdsdi_insert_crc
    port (
        insert_crc: in  std_logic;      -- CRC valaues will be inserted when this input is high
        crc_word0:  in  std_logic;      -- input asserted during time for first CRC word in EAV
        crc_word1:  in  std_logic;      -- input asserted during time for second CRC word in EAV
        c_in:       in  hd_video_type;  -- C channel video input
        y_in:       in  hd_video_type;  -- Y channel video input
        c_crc:      in  hd_crc18_type;  -- C channel CRC value input
        y_crc:      in  hd_crc18_type;  -- Y channel CRC value input
        c_out:      out hd_video_type;  -- C channel video output
        y_out:      out hd_video_type   -- Y channel video output
    );
end component;

component hdsdi_encoder
    port (
        clk:        in  std_logic;      -- word rate clock (74.25 MHz)
        rst:        in  std_logic;      -- async reset
        ce:         in  std_logic;      -- clock enable
        nrzi:       in  std_logic;      -- 1 enables NRZ-to-NRZI conversion
        scram:      in  std_logic;      -- 1 enables SDI scrambler
        c:          in  hd_video_type;  -- C channel input data port
        y:          in  hd_video_type;  -- Y channel input data port
        q:          out hd_vid20_type); -- output data port
end component; 

component hdsdi_crc
    port (
        clk:        in  std_logic;      -- word rate clock (74.25 MHz)
        ce:         in  std_logic;      -- clock enable
        rst:        in  std_logic;      -- async reset
        clr:        in  std_logic;      -- assert during first cycle of CRC calc
        d:          in  hd_video_type;  -- video word input
        crc_out:    out hd_crc18_type); -- CRC output value
end component;

begin

    --
    -- EAV delay register
    --
    -- Generates timing control signals for line number insertion and CRC generation
    -- and insertion.
    --
    process(clk, rst)
    begin
        if rst = '1' then
            eav_dly <= (others => '0');
        elsif clk'event and clk = '1' then
            if ce = '1' then
                eav_dly <= (eav_dly(2 downto 0) & eav);
            end if;
        end if;
    end process;

    --
    -- Instantiate the line number formatting and insertion module
    --
    INS_LN : hdsdi_insert_ln
        port map (
            insert_ln       => insert_ln,
            ln_word0        => eav_dly(0),
            ln_word1        => eav_dly(1),
            c_in            => c_in,
            y_in            => y_in,
            ln              => ln,
            c_out           => c_ln_out,
            y_out           => y_ln_out
        );
            

    --
    -- Generate timing control signals for the CRC calculators.
    --
    -- The crc_en signal determines which words are included into the CRC 
    -- calculation. All words that enter the hdsdi_crc module when crc_en is high
    -- are included in the calculation. To meet the HD-SDI spec, the CRC calculation
    -- must being with the first word after the SAV and end after the second line
    -- number word after the EAV.
    --
    -- The clr_crc signal clears the internal registers of the hdsdi_crc modules to
    -- cause a new CRC calculation to begin. The crc_en signal is asserted during
    -- the XYZ word of the SAV since the next word after the SAV XYZ word is the
    -- first word to be included into the new CRC calculation.
    --
    process(clk, rst)
    begin
        if rst = '1' then
            crc_en <= '0';
        elsif clk'event and clk = '1' then
            if ce = '1' then
                if sav = '1' then
                    crc_en <= '1';
                elsif eav_dly(1) = '1' then
                    crc_en <= '0';
                end if;
            end if;
        end if;
    end process;

    process(clk, rst)
    begin
        if rst = '1' then
            clr_crc <= '0';
        elsif clk'event and clk = '1' then
            if ce = '1' then
                clr_crc <= sav;
            end if;
        end if;
    end process;

    --
    -- Instantiate the CRC generators
    --
    crc_en_ce <= ce and crc_en;

    C_CRC : hdsdi_crc
        port map (
            clk             => clk,
            ce              => crc_en_ce,
            rst             => rst,
            clr             => clr_crc,
            d               => c_ln_out,
            crc_out         => c_crc_calc
        );

    Y_CRC : hdsdi_crc
        port map (
            clk             => clk,
            ce              => crc_en_ce,
            rst             => rst,
            clr             => clr_crc,
            d               => y_ln_out,
            crc_out         => y_crc_out
        );

    --
    -- Force a C channel CRC error if force_crc_err is asserted by inverting the 
    -- LSB of the calculated C channel CRC value.
    --
    c_crc_out <= (c_crc_calc(17 downto 1) & (c_crc_calc(0) xor force_crc_err));

    --
    -- Insert the CRC values into the Y and C channels. The CRC values are inserted
    -- after the line number words after the EAV.
    --
    CRC : hdsdi_insert_crc
        port map (
            insert_crc      => insert_crc,
            y_in            => y_ln_out,
            c_in            => c_ln_out,
            crc_word0       => eav_dly(2),
            crc_word1       => eav_dly(3),
            y_crc           => y_crc_out,
            c_crc           => c_crc_out,
            y_out           => y_crc_ins_out,
            c_out           => c_crc_ins_out
        );

    --
    -- Instantiate the SMPTE 292M encoder
    --
    ENC : hdsdi_encoder
        port map (
            clk            => clk,
            rst            => rst,
            ce             => ce,
            nrzi           => nrzi,
            scram          => scram,
            c              => c_crc_ins_out,
            y              => y_crc_ins_out,
            q              => q
        );

end synth;