hdsdi_encoder.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hdsdi_encoder.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-12-15 11:14:31-07 $
// /___/   /\    Date Created: May 28, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hdsdi_encoder.v,rcs $
// Revision 1.1  2004-12-15 11:14:31-07  jsnow
// Header update.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This module is the top-level module of the HD-SDI scrambler. This module encodes
20-bits of data, 10-bits of chroma (C) and 10-bits of luma (Y), per clock cycle.
There is a three clock cycle latency through the module.

This module instantiates the smpte_encoder module twice, with one module 
encoding the C data and the other the Y data. The two modules are cross 
connected so that the results from one encoder affects the encoding of the bits
in the other encoder, as required by the HD-SDI encoding scheme.

The q output is a 20-bit encoded value. Note that this value must be bit-swapped
before it can be connected to the 20-bit input of the RocketIO transmitter.
--------------------------------------------------------------------------------
*/

module hdsdi_encoder (
    clk,                // input clock
    rst,                // reset signal
    ce,                 // input register load signal
    nrzi,               // enables NRZ-to-NRZI conversion when high
    scram,              // enables SDI scrambler when high
    c,                  // C channel input data
    y,                  // Y channel input data 
    q                   // encoded output data
);

// IO definitions   
input               clk;
input               rst;
input               ce;
input               nrzi;
input               scram; 
input   [9:0]       c;
input   [9:0]       y;
output  [19:0]      q;

// Internal registers
reg     [9:0]       c_in_reg;
reg     [9:0]       y_in_reg;

// Internal wires
wire    [8:0]       c_i_scram;  // C channel intermediate scrambled data
wire    [8:0]       y_i_scram_q;// Y channel intermediate scrambled data
wire                c_i_nrzi;   // C channel intermediate nrzi data
wire    [9:0]       c_out;      // output of C scrambler
wire    [9:0]       y_out;      // output of Y scrambler

//
// Scrambler modules for both C and Y channels
//
smpte_encoder C_scram (
    .clk        (clk),
    .rst        (rst),
    .ce         (ce),
    .nrzi       (nrzi),
    .scram      (scram),
    .d          (c_in_reg),
    .p_scram    (y_i_scram_q),
    .p_nrzi     (y_out[9]),
    .q          (c_out),
    .i_scram    (c_i_scram),
    .i_scram_q  (),
    .i_nrzi     (c_i_nrzi)
);

smpte_encoder Y_scram (
    .clk        (clk),
    .rst        (rst),
    .ce         (ce),
    .nrzi       (nrzi),
    .scram      (scram),
    .d          (y_in_reg),
    .p_scram    (c_i_scram),
    .p_nrzi     (c_i_nrzi),
    .q          (y_out),
    .i_scram    (),
    .i_scram_q  (y_i_scram_q),
    .i_nrzi     ()
);

//
// Input registers
//
always @ (posedge clk or posedge rst)
    if (rst)
        begin
            c_in_reg <= 0;
            y_in_reg <= 0;
        end
    else if (ce)
        begin
            c_in_reg <= c;
            y_in_reg <= y;
        end

//
// Output assignment
//
assign q = {y_out, c_out};

endmodule