hdsdi_rx_timing.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2005 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hdsdi_rx_timing.v,rcs $
//  /   /        Date Last Modified:  $Date: 2005-01-14 10:53:12-07 $
// /___/   /\    Date Created: Jan 5, 2005 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hdsdi_rx_timing.v,rcs $
// Revision 1.1  2005-01-14 10:53:12-07  jsnow
// Header update.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This module is a simple HD-SDI video decoder module. It will generate various
video timing outputs. It is not a sophisticated video flywheel decoder. It 
relies of video line number information that has been extracted from the video
by the hdsdi_rx_crc module. This module is not required for the basic HD-SDI
receiver. It is provided here in case some downstream video processing needs
the timing information that it can generate.

The outputs generated by this module are:

frame_start: This output indicates when a new frame is starting. It is asserted
during the entire horizontal blanking intervarl of line number 1.

field: This is captured F bit from the last TRS symbol.

v_blank: This is the captured V bit from the last TRS symbol.

h_blank: This is the captured H bit from the last TRS symbol.

horz_position: This output represents the current horizontal position of the
video. It resets to zero at the end of each SAV and then increments every clock
cycle.

--------------------------------------------------------------------------------
*/

module hdsdi_rx_timing (
    clk,                            // input clock
    rst,                            // async reset
    ln_in,                          // 11-bit line number
    vid_in,                         // 10-bit input video
    xyz,                            // input asserted during XYZ word of TRS
    sav,                            // input asserted during XYZ word of SAV
    frame_start,                    // asserted during h blank when ln = 1
    field,                          // field indicator
    v_blank,                        // asserted during vertical blanking interval
    h_blank,                        // asserted during horizontal blanking interval
    horz_position                   // 12-bit horizontal position
);


// IO definitions   
input               clk;
input               rst;
input   [10:0]      ln_in;
input   [9:0]       vid_in;
input               xyz;
input               sav;
output              frame_start;
output              field;
output              v_blank;
output              h_blank;
output  [11:0]      horz_position;


// Internal signals
reg                 f;              // F bit register
reg                 v;              // V bit register
reg                 h;              // H bit register
reg     [11:0]      h_count;        // horzontal position counter


//
// H, V, and F bit registers
//
always @ (posedge clk or posedge rst)
    if (rst)
        begin
            f <= 1'b0;
            v <= 1'b0;
            h <= 1'b0;
        end
    else if (xyz)
        begin
            f <= vid_in[8];
            v <= vid_in[7];
            h <= vid_in[6];
        end

assign field   = f;
assign v_blank = v;
assign h_blank = h;


//
// Horzontal position counter
//
always @ (posedge clk or posedge rst)
    if (rst)
        h_count <= 0;
    else
        if (sav)
            h_count <= 0;
        else
            h_count <= h_count + 1;

assign horz_position = h_count;

//
// frame_start output logic
//
assign frame_start = (ln_in == 1) & h;

endmodule