multigenhd_output.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

CROM.INIT_2F = 256'h008001000080010000C0064000C0064000C0066000C0066000C0066000C00660,
CROM.INIT_30 = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_31 = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_32 = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_33 = 256'h0080044000800440008001000080010000800100008001000080010000800100,
CROM.INIT_34 = 256'h0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC,
CROM.INIT_35 = 256'h00C70C7000000000008001000080010000800100008001000080080000000000,
CROM.INIT_36 = 256'h00DA0DA000000000008001000080010000800100008001000080010000800100,
CROM.INIT_37 = 256'h0080010000800100008004400080044000800440008004400080044000800440,
CROM.INIT_38 = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_39 = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_3A = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_3B = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_3C = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_3D = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_3E = 256'h0080010000800100008001000080010000800100008001000080010000800100,
CROM.INIT_3F = 256'h0080010000800100008001000080010000800100008001000080010000800100;
//synthesis translate_on

RAMB16_S36 CROM (
    .DO     (crom_out),
    .DOP    (),
    .ADDR   ({v_band, h_region, h_counter_lsb}),
    .CLK    (clk),
    .DI     (GND32),
    .DIP    (GND4),
    .EN     (1'b1),
    .SSR    (rst),
    .WE     (1'b0));

// XST synthesis initialization code CROM
// Created by multigenHD_romgen.v
// Video format mapping:
//   000 =  SMPTE 295M - 1080i  25Hz (1250 lines/frame)
//   001 =  SMPTE 274M - 1080sF 24Hz & 23.98Hz         
//   002 =  SMPTE 274M - 1080i  30Hz & 29.97 Hz        
//   003 =  SMPTE 274M - 1080i  25Hz                   
//   004 =  SMPTE 274M - 1080p  30Hz & 29.97Hz         
//   005 =  SMPTE 274M - 1080p  25Hz                   
//   006 =  SMPTE 274M - 1080p  24Hz & 23.98Hz         
//   007 =  SMPTE 296M - 720p   60Hz & 59.94Hz         
//synthesis attribute INIT of CROM is "000800100"
//synthesis attribute SRVAL of CROM is "000800100"
//synthesis attribute WRITE_MODE of CROM is "READ_FIRST"
//synthesis attribute INITP_00 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_01 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_02 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_03 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_04 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_05 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_06 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INITP_07 of CROM is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_00 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_01 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_02 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_03 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_04 of CROM is "0000000000FFCFFC008001000080010000B60B60000000000000000000FFCFFC"
//synthesis attribute INIT_05 of CROM is "00EC0EC0000000000080010000800100008001000080010000AB0AB000000000"
//synthesis attribute INIT_06 of CROM is "00F10F1000000000008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_07 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_08 of CROM is "0087CA88002C0A880087CA88002C0A8800800B4400800B440080067800800678"
//synthesis attribute INIT_09 of CROM is "00CC43EC00C0C3EC0033C858003F48580033C858003F4858002C091400934914"
//synthesis attribute INIT_0A of CROM is "00D40330006CC33000D40330006CC33000CC43EC00C0C3EC00CC43EC00C0C3EC"
//synthesis attribute INIT_0B of CROM is "00800678008006780080067800800678007841BC00D401BC00D40330006CC330"
//synthesis attribute INIT_0C of CROM is "0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC"
//synthesis attribute INIT_0D of CROM is "00C70C7000000000008001000080010000800100008001000080080000000000"
//synthesis attribute INIT_0E of CROM is "00DA0DA00000000000800B4400800B4400800B4400800B4400800B4400800B44"
//synthesis attribute INIT_0F of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_10 of CROM is "00800B4400800B4400800B4400800B4400800B4400800B4400100BC80099CBC8"
//synthesis attribute INIT_11 of CROM is "00800B4400800B4400800B4400800B4400800B4400800B4400800B4400800B44"
//synthesis attribute INIT_12 of CROM is "00800B4400800B4400800B4400800B4400800B4400800B4400800B4400800B44"
//synthesis attribute INIT_13 of CROM is "0075C1FC00F001FC0075C1FC00F001FC00800B4400800B4400800B4400800B44"
//synthesis attribute INIT_14 of CROM is "0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC"
//synthesis attribute INIT_15 of CROM is "00C70C7000000000008001000080010000800100008001000080080000000000"
//synthesis attribute INIT_16 of CROM is "00DA0DA0000000000062C3D0009903D0009D43D4006703D400800EB000800EB0"
//synthesis attribute INIT_17 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_18 of CROM is "00800EB200800EB200800EB200800EB20080010100800101008A4DB400100DB4"
//synthesis attribute INIT_19 of CROM is "00800EB200800EB200800EB200800EB200800EB200800EB200800EB200800EB2"
//synthesis attribute INIT_1A of CROM is "00800EB200800EB200800EB200800EB200800EB200800EB200800EB200800EB2"
//synthesis attribute INIT_1B of CROM is "00F003E8006643E800F003E8006643E800800EB200800EB200800EB200800EB2"
//synthesis attribute INIT_1C of CROM is "0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC"
//synthesis attribute INIT_1D of CROM is "00C70C7000000000008001000080010000800100008001000080080000000000"
//synthesis attribute INIT_1E of CROM is "00DA0DA0000000000097823500AE423500800101008001010080010100800101"
//synthesis attribute INIT_1F of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_20 of CROM is "00800EB000800EB0008001000080010000800100008001000080030C0080030C"
//synthesis attribute INIT_21 of CROM is "0080010000800100008001000080010000800EB000800EB000800EB000800EB0"
//synthesis attribute INIT_22 of CROM is "008001000080010000800148008001480080010000800100008000B8008000B8"
//synthesis attribute INIT_23 of CROM is "0080030C0080030C0080030C0080030C00800100008001000080018C0080018C"
//synthesis attribute INIT_24 of CROM is "0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC"
//synthesis attribute INIT_25 of CROM is "00C70C7000000000008001000080010000800100008001000080080000000000"
//synthesis attribute INIT_26 of CROM is "00DA0DA000000000008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_27 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_28 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_29 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_2A of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_2B of CROM is "00C0066000C00660008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_2C of CROM is "0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC"
//synthesis attribute INIT_2D of CROM is "00C70C7000000000008001000080010000800100008001000080080000000000"
//synthesis attribute INIT_2E of CROM is "00DA0DA000000000008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_2F of CROM is "008001000080010000C0064000C0064000C0066000C0066000C0066000C00660"
//synthesis attribute INIT_30 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_31 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_32 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_33 of CROM is "0080044000800440008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_34 of CROM is "0000000000FFCFFC0080010000800100009D09D0000000000000000000FFCFFC"
//synthesis attribute INIT_35 of CROM is "00C70C7000000000008001000080010000800100008001000080080000000000"
//synthesis attribute INIT_36 of CROM is "00DA0DA000000000008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_37 of CROM is "0080010000800100008004400080044000800440008004400080044000800440"
//synthesis attribute INIT_38 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_39 of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_3A of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_3B of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_3C of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_3D of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_3E of CROM is "0080010000800100008001000080010000800100008001000080010000800100"
//synthesis attribute INIT_3F of CROM is "0080010000800100008001000080010000800100008001000080010000800100"

assign y_ramp_reload = crom_out[0];
assign y_ramp_en = crom_out[1];
assign y_rom = crom_out[VID_MSB+2:2];
assign c_rom = crom_out[VID_MSB+14:14];

//
// Y Ramp increment selection
//
// This MUX selects the Y Ramp increment value. Different increment values are
// used for formats with 1920 active samples per line vs. 1280 active samples
// per line. This is because the Y Ramp pattern contains less samples if there
// are only 1280 active samples per line, so the increment value must be
// bigger in order to reach the maximum Y value by the end of the Y Ramp
// pattern.
//
// The control for this MUX comes from an output of the VROM. The VROM decodes
// the std input code and controls this MUX appropriately.
//
assign y_ramp_inc = y_ramp_inc_sel ? Y_INC_1280 : Y_INC_1920;

//
// Y Ramp register & adder
//
// This is the accumulator section of the Y Ramp generator. The register
// normally accumulates new Y Ramp increment values with the current contents
// of the register every clock cycle. However, if the y_ramp_reload output of
// the CROM is asserted, the register is loaded with the YRAMP_INIT value to
// begin the Y_RAMP pattern. The accumulator contains 10 integer bits and 7
// fractional bits to make a smooth ramp function.
//
always @ (posedge clk or posedge rst)
    if (rst)
        y_ramp <= YRAMP_INIT;
    else if (ce)
        begin
            if (y_ramp_reload)
                y_ramp <= YRAMP_INIT;
            else
                y_ramp <= y_ramp + y_ramp_inc;
        end

//
// Y Ramp rounder
//
// This code rounds the output of the Y Ramp accumulator to the nearest integer
// by adding a value of 0.5 and then truncating the fractional bits.
//
assign y_ramp_round = y_ramp + YRAMP_RND;
assign y_ramp_out = y_ramp_round[YRAMP_MSB:(YRAMP_MSB - VID_WIDTH) + 1];

//
// Y output mux
//
// This MUX will normally output the Y value from the CROM unless the Y Ramp
// pattern is being shown, in which case it outputs the rounded output of the
// Y Ramp accumulator.
//
assign y_ramp_mux = y_ramp_en ? y_ramp_out : y_rom;

assign y = y_ramp_mux;
assign c = c_rom;

endmodule