multigenhd_logo.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//
// The rom_adr_v counter initializes to a value of 81 for 1080p, 720p, and the first
// field of 1080i whenever logo_en_v is not asserted, indicating the current
// line does not contain the logo. For the second field of 1080i, the counter
// loads with 80. For all lines during which logo_en_v is asserted, the counter
// is decremented by 1 for progressive formats or 2 for interlaced formats. This
// occurs during the second word of the SAV (sav asserted). Note that the
// counter won't decrement on the first active logo line because logo_en_v
// doesn't become asserted until the clock after sav is asserted.
//
always @ (posedge clk)
    if (ce)
        begin
            if (~logo_en_v & ~f_int)
                rom_adr_v <= 81;
            else if (~logo_en_v & f_int)
                rom_adr_v <= 80;
            else if (logo_en_v & sav)
                rom_adr_v <= rom_adr_v - (is1080i ? 2 : 1);
        end

//
// Logo ROM address H counter
//
// The rom_adr_h counter is cleared to zero whenever logo_en is not asserted.
// It increments by 1 whenever log_en is asserted.
// 
always @ (posedge clk)
    if (ce)
        begin
            if (~logo_en)
                rom_adr_h <= 0;
            else
                rom_adr_h <= rom_adr_h + 1;
        end

//
// Logo address multiplier
//
// This multiplier multiplies the logo width times the current rom_adr_v
// value. Subsequently, the rom_adr_h is added to the product to create the
// actual address to the logo ROM.
//

assign logo_mult_a = {11'b0, rom_adr_v};
assign logo_mult_b = LOGO_WIDTH;

`ifdef VIRTEX4

DSP48 #(
    .AREG           (0),
    .BREG           (0),
    .B_INPUT        ("DIRECT"),
    .CARRYINREG     (0),
    .CARRYINSELREG  (0),
    .CREG           (0),
    .LEGACY_MODE    ("MULT18X18"),
    .MREG           (0),
    .OPMODEREG      (0),
    .PREG           (0),
    .SUBTRACTREG    (0))
LOGOMULT (
    .A              (logo_mult_a),
    .B              (logo_mult_b),
    .BCIN           (18'd0),
    .C              ({39'd0, rom_adr_h}),
    .CARRYIN        (1'b0),
    .CARRYINSEL     (2'b00),
    .CEA            (1'b0),
    .CEB            (1'b0),
    .CEC            (1'b0),
    .CECARRYIN      (1'b0),
    .CECINSUB       (1'b0),
    .CECTRL         (1'b0),
    .CEM            (1'b0),
    .CEP            (1'b0),
    .CLK            (1'b0),
    .OPMODE         (7'h35),
    .PCIN           (48'd0),
    .RSTA           (1'b0),
    .RSTB           (1'b0),
    .RSTC           (1'b0),
    .RSTCARRYIN     (1'b0),
    .RSTCTRL        (1'b0),
    .RSTM           (1'b0),
    .RSTP           (1'b0),
    .SUBTRACT       (1'b0),
    .BCOUT          (),
    .P              (logo_mult_p),
    .PCOUT          ());

assign rom_adr =logo_mult_p[14:0];

`else

MULT18X18 LOGOMULT (
    .P      (logo_mult_p),
    .A      (logo_mult_a),
    .B      (logo_mult_b));


assign rom_adr_mult = logo_mult_p[14:0];
assign rom_adr = rom_adr_mult + rom_adr_h;

`endif

//
// This logic converts the 0 to 255 grayscale value from the logo ROM to a
// Y component with a value from 64 to 940. The ROM output value is multiplied
// by fixed point binary value with 8 fractional bits. this value is approximately
// equal to (940 - 64) / 255 thus scaling the 0 to 255 value to 0 to 876 (940 - 64).
// Next, the output of the multiplier is rounded to the nearest integer and then
// 64 is added to offset the Y component to be between 64 and 940.
//

assign logo_mult2_a = {10'b0, lrom_out};
assign logo_mult2_b = {18'b0000_0000_11_01101111}; // 8 fractional bits

`ifdef VIRTEX4

DSP48 #(
    .AREG           (0),
    .BREG           (0),
    .B_INPUT        ("DIRECT"),
    .CARRYINREG     (0),
    .CARRYINSELREG  (0),
    .CREG           (0),
    .LEGACY_MODE    ("MULT18X18"),
    .MREG           (0),
    .OPMODEREG      (0),
    .PREG           (0),
    .SUBTRACTREG    (0))
LOGOMULT2 (
    .A              (logo_mult2_a),
    .B              (logo_mult2_b),
    .BCIN           (18'd0),
    .C              (48'h0407f),        // rounding bits + 64 * 256
    .CARRYIN        (1'b0),
    .CARRYINSEL     (2'b00),
    .CEA            (1'b0),
    .CEB            (1'b0),
    .CEC            (1'b0),
    .CECARRYIN      (1'b0),
    .CECINSUB       (1'b0),
    .CECTRL         (1'b0),
    .CEM            (1'b0),
    .CEP            (1'b0),
    .CLK            (1'b0),
    .OPMODE         (7'h35),
    .PCIN           (48'd0),
    .RSTA           (1'b0),
    .RSTB           (1'b0),
    .RSTC           (1'b0),
    .RSTCARRYIN     (1'b0),
    .RSTCTRL        (1'b0),
    .RSTM           (1'b0),
    .RSTP           (1'b0),
    .SUBTRACT       (1'b0),
    .BCOUT          (),
    .P              (logo_Y_sum),
    .PCOUT          ());

assign logo_Y = logo_Y_sum[17:8];

`else
        
MULT18X18 LOGOMULT2 (
    .P      (logo_mult2_p),
    .A      (logo_mult2_a),
    .B      (logo_mult2_b));

assign logo_Y_sum = logo_mult2_p[17:0] + 18'b0000_0000_00_01111111; // rounder
assign logo_Y = logo_Y_sum[17:8] + 10'd64;                      // offset by 64

`endif

//
// These MUXes will substitute the logo video sample for the normal video
// sample when logo_en is asserted. The Y component of the logo is computed
// above. The C component of the logo is always 512.
//
assign logo_out_mux_Y = (insert_logo & logo_en_dly) ? logo_Y : y_int;
assign logo_out_mux_C = (insert_logo & logo_en_dly) ? 10'd512 : c_int;

//
// This MUX select which ROM output is used based on the MS 4 bits of the ROM 
// address. Note that because the 11 LS bits of the address are effectively 
// delayed by one clock cycle at the input register of the block RAMs, the MS 
// address bits that control this MUX must also be delayed by one clock cycle 
// before being applied to the MUX control signals.
//
assign arom_adr = rom_adr;
assign brom_adr = 15'd0;

always @ (posedge clk)
    arom_adr_ms_dly <= arom_adr[14:11];

always @ *
    case(arom_adr_ms_dly)
        4'b0000: lrom_out <= arom0_out;
        4'b0001: lrom_out <= arom1_out;
        4'b0010: lrom_out <= arom2_out;
        4'b0011: lrom_out <= arom3_out;
        4'b0100: lrom_out <= arom4_out;
        4'b0101: lrom_out <= arom5_out;
        4'b0110: lrom_out <= arom6_out;
        4'b0111: lrom_out <= arom7_out;
        4'b1000: lrom_out <= arom8_out;
        4'b1001: lrom_out <= arom9_out;
        4'b1010: lrom_out <= arom10_out;
        default: lrom_out <= arom0_out;
    endcase

// 
// Xilinx Logo Block RAMs
//
RAMB16_S9_S9 HDROM0 (
    .DOA    (arom0_out),
    .DOB    (),
    .DOPA   (),
    .DOPB   (),
    .ADDRA  (arom_adr[10:0]),