shixu.vhd

来自「自己 写的课程设计」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity SHIXU is
port(clk:in std_logic;
TG:in std_logic;
start:in std_logic;
SHUCHU:BUFFER std_logic_VECTOR(2 DOWNTO 0)
);
end SHIXU; 
architecture behav of SHIXU is
SIGNAL QQ:STD_LOGIC_VECTOR(5 DOWNTO 0);
begin
process(clk,tg)
begin
if(tg='1')or(start='0') then shuchu<="000";
elsif(clk'event) and (clk='1')then
  iF(QQ=39)THEN 
    if(shuchu=6)then shuchu<="001";
    else shuchu<=shuchu+1;
    end if;   
    QQ<="000000";
  
      ELSE QQ<=QQ+1;
  END IF;
  END IF;


END PROCESS;
end behav;