yuzhi.vhd

自己 写的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

library Altera;
use Altera.maxplus2.all;


entity zongxianshi is
port(LD:IN std_logic;
CLK:IN STD_LOGIC;
CP:IN std_logic;
START:IN std_logic;
seg1,seg2,seg3,seg4:out std_logic_vector(6 downto 0);
getdata,getdatajishu:buffer std_logic_vector(7 downto 0);
tJ:BUFFER std_logic;
run:out std_logic;
rev:out std_logic;
pause:out std_logic
);
end zongxianshi; 
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='0')or(k1='1')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='0')or(k1='0')or(k2='1')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))
or((k0='1')or(k1='0')or(k2='0')
or(k3='0')
or(k4='0')
or(k5='0')
or(k6='0')
or(k7='0')
or(k8='0')
or(k9='0'))