7duan.vhd

自己 写的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity xianshi is
port(getdata:IN std_logic_vector(7 downto 0);
seg1:out std_logic_vector(6 downto 0);
seg2:out std_logic_vector(6 downto 0));
end xianshi; 
architecture behav of xianshi is
begin

SEG1 <= "0111111" WHEN getdata(7 downto 4) = "0000" ELSE
"0000110" WHEN getdata(7 downto 4) = "0001"ELSE
"1011011" WHEN getdata(7 downto 4) = "0010" ELSE
"1001111" WHEN getdata(7 downto 4) = "0011" ELSE
"1100110" WHEN getdata(7 downto 4) = "0100" ELSE
"1101101" WHEN getdata(7 downto 4) = "0101" ELSE
"1111101" WHEN getdata(7 downto 4) = "0110" ELSE
"0000111" WHEN getdata(7 downto 4) = "0111" ELSE
"1111111" WHEN getdata(7 downto 4) = "1000" ELSE
"1101111" WHEN getdata(7 downto 4) = "1001" ELSE
"1110111" WHEN getdata(7 downto 4) = "1010" ELSE
"1111100" WHEN getdata(7 downto 4) = "1011" ELSE
"0111001" WHEN getdata(7 downto 4) = "1100" ELSE
"1011110" WHEN getdata(7 downto 4) = "1101" ELSE
"1111001" WHEN getdata(7 downto 4) = "1110" ELSE
"1110001" WHEN getdata(7 downto 4) = "1111" ELSE
"0000000";
SEG2 <= "0111111" WHEN getdata(3 downto 0) = "0000" ELSE
"0000110" WHEN getdata(3 downto 0) = "0001"ELSE
"1011011" WHEN getdata(3 downto 0) = "0010" ELSE
"1001111" WHEN getdata(3 downto 0) = "0011" ELSE
"1100110" WHEN getdata(3 downto 0) = "0100" ELSE
"1101101" WHEN getdata(3 downto 0) = "0101" ELSE
"1111101" WHEN getdata(3 downto 0) = "0110" ELSE
"0000111" WHEN getdata(3 downto 0) = "0111" ELSE
"1111111" WHEN getdata(3 downto 0) = "1000" ELSE
"1101111" WHEN getdata(3 downto 0) = "1001" ELSE
"1110111" WHEN getdata(3 downto 0) = "1010" ELSE
"1111100" WHEN getdata(3 downto 0) = "1011" ELSE
"0111001" WHEN getdata(3 downto 0) = "1100" ELSE
"1011110" WHEN getdata(3 downto 0) = "1101" ELSE
"1111001" WHEN getdata(3 downto 0) = "1110" ELSE
"1110001" WHEN getdata(3 downto 0) = "1111" ELSE
"0000000";

End behav;