jishu.vhd

来自「自己 写的课程设计」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity JISHU is
port(LD:IN std_logic;
cP:IN std_logic;
JISHUtime:BUFFER integer range 0 to 255);
end JISHU; 
architecture behav of JISHU is
begin
process(cP)
begin
IF(CP'EVENT AND CP='1')THEN
  if(ld='1')then
   if(JISHUtime=99)then JISHUtime<=0;
  else JISHUTIME<=JISHUTIME+1;
 END IF;
end if;
end if;
end process;
end behav;