yima.vhd

来自「自己 写的课程设计」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity YIMA is
port(run:out std_logic;
rev:out std_logic;
pause:out std_logic;
SHURU:IN std_logic_VECTOR(2 DOWNTO 0)
);
end YIMA; 
architecture behav of yima is
begin
process(shuru)
begin
if(SHURU="001")OR(SHURU="010")THEN rev<='0';run<='1';pause<='0';
elsif(SHURU="011")THEN rev<='0';run<='0';pause<='1';
elsif(SHURU="100")OR(SHURU="101")THEN rev<='1';run<='0';pause<='0';
elsif(SHURU="110")THEN rev<='0';run<='0';pause<='1';
else rev<='0';run<='0';pause<='0';
end if;
end process;
end behav;