chengfaqi.txt

本源码是高速并行乘法器的设计源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY traffic_control IS
  PORT(
       clk:IN STD_LOGIC;
       c1,c2,c3:OUT STD_LOGIC;
       w1,w2,w3:IN STD_LOGIC;
        r1,r2:OUT STD_LOGIC;
       y1,y2:OUT STD_LOGIC;
       g1,g2:OUT STD_LOGIC;
       reset:IN STD_LOGIC);
   END traffic_control;

ARCHITECTURE a OF traffic_control IS
 TYPE STATE_SPACE IS(S0,S1,S2,S3);
 SIGNAL  state:STATE_SPACE;
 BEGIN
   PROCESS(clk)
   BEGIN
     IF reset='1'THEN
       state<=s0;
     	ELSIF(clk 'EVENT AND clk='1')THEN
              CASE state IS
                  WHEN S0=>
                         IF w1='1'THEN
                             state<=S1;
                         END IF;
                 WHEN S1=>
                         IF w2='1'THEN
                             state<=S2;
                         END IF;
                 WHEN S2=>
                         IF w3='1'THEN
                             state<=S3;
                         END IF;
                 WHEN S3=>
                         IF w2='1'THEN
                             state<=S0;
                         END IF;
              END CASE;
        END IF;
  END PROCESS;
  c1<='1' WHEN state=S0 ELSE'0';
  c2<='1' WHEN state=S1 OR state=S3 ELSE'0';
  c3<='1' WHEN state=S2 ELSE'0';
  r1<='1' WHEN state=S1 OR state=S0 ELSE'0';
  y1<='1' WHEN state=S3 ELSE'0';
  g1<='1' WHEN state=S2 ELSE'0';
  r2<='1' WHEN state=S2 OR state=S3 ELSE'0';
  y2<='1' WHEN state=S1 ELSE'0';
  g2<='1' WHEN state=S0 ELSE'0';
END a;
 


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY count30 IS
  PORT(
       clk:IN STD_LOGIC;
       enable:IN STD_LOGIC;
       c:OUT STD_LOGIC);
   END count30;

ARCHITECTURE a OF count30 IS
BEGIN
   PROCESS(clk)
      VARIABLE cnt:INTEGER RANGE 30 DOWNTO 0;
  BEGIN
     IF(clk 'EVENT AND clk='1')THEN
       IF enable='1' AND cnt<30 THEN
           cnt:=cnt+1;
       ELSE
           cnt:=0;
       END IF;
      END IF;
    IF cnt=30 THEN
       C<='1';
    ELSE
       C<='0';
    END IF;
    END PROCESS;
   END a;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY count05 IS
  PORT(
       clk:IN STD_LOGIC;
       enable:IN STD_LOGIC;
       c:OUT STD_LOGIC);
   END count05;
ARCHITECTURE a OF count05 IS
BEGIN
   PROCESS(clk)
      VARIABLE cnt:INTEGER RANGE 5 DOWNTO 0;
  BEGIN
     IF(clk 'EVENT AND clk='1')THEN
       IF enable='1'AND cnt<5 THEN
           cnt:=cnt+1;
       ELSE
           cnt:=0;
       END IF;
      END IF;
    IF cnt=5 THEN
       C<='1';
    ELSE
       C<='0';
    END IF;

  END PROCESS;
END a;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY count26 IS
  PORT(
       clk:IN STD_LOGIC;
       enable:IN STD_LOGIC;
       c:OUT STD_LOGIC);
   END count26;
ARCHITECTURE a OF count26 IS
BEGIN
   PROCESS(clk)
      VARIABLE cnt:INTEGER RANGE 26 DOWNTO 0;
  BEGIN
     IF(clk 'EVENT AND clk='1')THEN
       IF enable='1'AND cnt<26 THEN
           cnt:=cnt+1;
       ELSE
           cnt:=0;
       END IF;
     END IF;
    IF cnt=26 THEN
       C<='1';
    ELSE
       C<='0';
    END IF;
  END PROCESS;
END a;