divid_8.v

verilog 的东西好好用的呢

// divided by 8 with shif right operator ">>"
//filename : divid_8
module divid_8(quot, div);

output [7:0] quot;  //quotient
input  [7:0] div;   //dividend

parameter sh_bit = 3; //define the number of bits for shifting 

assign quot = div >> sh_bit;

endmodule