major.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 13 行

//-------------------------------
//Majority with bitwise operators
//Filename : major.v
//-------------------------------
module major(maj, I);
output maj;
input [2:0] I;

//Assign majority output with I
assign maj = (I[1] & I[0]) | (I[2] & (I[1] | I[0]));

endmodule