adder4.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 15 行

//----------------------
//4-bit unsigned adder
//Filename : adder4.v
//----------------------                                                                                                                                                                                                                   
module adder4(S, Cout, A, B, Cin);
output [3:0] S;   //4-bit sum
output Cout;	   //Carry out
input [3:0] A, B; //Inputs
input Cin;	   //Carry in

//Assign the sum of (A+B+Cin) to Cout and Sum
assign {Cout, S} = A + B + Cin;

endmodule