decod3_8.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 21 行

//----------------------------------------------
//Low active 3-8 decoder usign bitwise operators
//Filename : decod3_8.v
//----------------------------------------------
module decod3_8(y, d);
output [7:0] y;
input [2:0] d;

 //compute the outputs with b
 assign y[0] = ~((~d[2]) & (~d[1]) & (~d[0])),
        y[1] = ~((~d[2]) & (~d[1]) & (d[0])),
        y[2] = ~((~d[2]) & (d[1]) & (~d[0])),
        y[3] = ~((~d[2]) & (d[1]) & (d[0])),
        y[4] = ~((d[2]) & (~d[1]) & (~d[0])),
        y[5] = ~((d[2]) & (~d[1]) & (d[0])),
        y[6] = ~((d[2]) & (d[1]) & (~d[0])),
        y[7] = ~((d[2]) & (d[1]) & (d[0]));


endmodule