fadd1_df.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 13 行

//-------------------------------------
//1-bit full subtractor with operators
//Filename : fadd1_df.v
//-------------------------------------
module fadd1_df(X, Y, Bin, Dif, Bout);
input X, Y, Bin;
output Dif, Bout;
//Assign difference and borrow
assign Dif = (((~X)&(~Y)&Bin)|((~X)&(Y)&(~Bin))|(X&(~Y)&(~Bin))|(X & Y & Bin));
assign Bout = (((~X)&Y)|((~X)&Bin)|(Y & Bin));

endmodule