even_parity.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 12 行

//check even parity and zeros
//filename : even_parity.v
module even_parity(ev_parity, all_zeros, din);

output ev_parity, all_zeros;
input [7:0] din;

assign ev_parity = ~^ din;
assign all_zeros = ~| din;

endmodule