mul2_1_4bits.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 15 行

//---------------------------------------------------
//4-bit 2 to 1 multiplexer using conditional operator
//filename : mul2_1_4bits.v
//---------------------------------------------------
module mul2_1_4bits(y, sel, a, b);

output [3:0] y;
input [3:0] a, b;       // 4-bit input data
input sel;                // selection line


assign y = (sel) ? a : b; 

endmodule