encod4_2.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 15 行

//-----------------------------------------------
//4-2 encoder using bitwise operators
//Filename : encod4_2.v
//-----------------------------------------------
module encod4_2(y, I3, I2, I1, I0);

output [1:0] y; 
input I3, I2, I1,I0;

//Assign y[1:0] with truth table states
assign y[1] = ((((~I3) & (I2)) | ((I3) & (~I2))) & (~I1) & (~I0)),
       y[0] = ((~I2) & (~I0) & (((~I3) & (I1)) | ((I3) & (~I1))));

endmodule