sht_r_l.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 22 行

//---------------------------------------------------------
//Shift right or left with 1 bits using concatenate operator
//Filename : sht_l_r.v
//---------------------------------------------------------
module sht_l_r(sht_out, din,l_r);
output [7:0] sht_out;
input [7:0] din;
input l_r;		    //l_r : selection of shift left or right

reg [7:0] cnt;

always @(l_r or din)
  begin
    cnt = din;
    if (l_r)
      cnt = {cnt[6:0], 1'b0}; //Shift left
    else
      cnt = {1'b0, cnt[7:1]}; //Shift right
  end
  assign sht_out = cnt;
endmodule