equ_inequ.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 16 行

module equ_inequ();
 reg [3:0] a, b, c, d, e, f;
 initial begin
    a=3; b=6;    // decimal values
    c = 4'b011;
    d = 4'bx11;
    e = 4'bx110;
    f = 4'bxx10;

    $display (a==b);  //logical equality, display (0)
    $display (c!=d);  //logical inequality, disply (x)
    $display (c!=f);  //logical inequality, display (1)
    $display (d===f); //conditionsl equality, display (0)
    $display (c!==d); //conditional inequality, display (1)
 end
endmodule