demul1_4.v

来自「verilog 的东西好好用的呢」· Verilog 代码 · 共 16 行

//----------------------------------------
//1-4 demultiplexer with bitwise operators
//Filename : demul1_4.v
//----------------------------------------
module demul1_4(y, I, S);
output [3:0] y;
input I;
input [1:0] S;     //Select signal

assign y[0] = (~S[1]) & (~S[0]) & I,
	  y[1] = (~S[1]) & (S[0]) & I,
	  y[2] = (S[1]) & (~S[0]) & I,
	  y[3] = (S[1]) & (S[0]) & I;

endmodule