__projnav.log

8位密码锁的实现

-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 52
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/mimasuo/fpq10ms.vhdl in Library work.
Architecture behavioral of Entity fpq10ms is up to date.
Compiling vhdl file e:/mimasuo/key.vhdl in Library work.
Architecture behavioral of Entity keyval is up to date.
Compiling vhdl file e:/mimasuo/SE8.vhdl in Library work.
Architecture behavioral of Entity se8 is up to date.
Compiling vhdl file e:/mimasuo/xzq81.vhdl in Library work.
Architecture behavioral of Entity xzq81 is up to date.
Compiling vhdl file e:/mimasuo/yiwei.vhdl in Library work.
Architecture behavioral of Entity yiwei is up to date.
Compiling vhdl file e:/mimasuo/fpq01ms.vhdl in Library work.
Architecture behavioral of Entity fpq01ms is up to date.
Compiling vhdl file e:/mimasuo/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file e:/mimasuo/bijiaoqi.vhdl in Library work.
Architecture behavioral of Entity bijiaoqi is up to date.
Compiling vhdl file e:/mimasuo/mimasuo.vhf in Library work.
Entity <mimasuo> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mimasuo> (Architecture <BEHAVIORAL>).
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 17: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 17: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 17: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/mimasuo/mimasuo.vhf line 17: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <mimasuo> analyzed. Unit <mimasuo> generated.

Analyzing Entity <fpq10ms> (Architecture <behavioral>).
Entity <fpq10ms> analyzed. Unit <fpq10ms> generated.

Analyzing Entity <keyval> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <rstcode> in unit <keyval> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <comp> in unit <keyval> never changes during circuit operation. The register is replaced by logic.
Entity <keyval> analyzed. Unit <keyval> generated.

Analyzing Entity <se8> (Architecture <behavioral>).
Entity <se8> analyzed. Unit <se8> generated.

Analyzing Entity <xzq81> (Architecture <behavioral>).
WARNING:Xst:819 - e:/mimasuo/xzq81.vhdl line 28: The following signals are missing in the process sensitivity list:
   Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1.
Entity <xzq81> analyzed. Unit <xzq81> generated.

Analyzing Entity <yiwei> (Architecture <behavioral>).
WARNING:Xst:819 - e:/mimasuo/yiwei.vhdl line 24: The following signals are missing in the process sensitivity list:
   clr, COUNT.
Entity <yiwei> analyzed. Unit <yiwei> generated.

Analyzing Entity <fpq01ms> (Architecture <behavioral>).
Entity <fpq01ms> analyzed. Unit <fpq01ms> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <bijiaoqi> (Architecture <behavioral>).
WARNING:Xst:819 - e:/mimasuo/bijiaoqi.vhdl line 77: The following signals are missing in the process sensitivity list:
   k1, k2, k3, k4, k5, k6, k7, k8.
INFO:Xst:1304 - Contents of register <cm> in unit <bijiaoqi> never changes during circuit operation. The register is replaced by logic.
Entity <bijiaoqi> analyzed. Unit <bijiaoqi> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <bijiaoqi>.
    Related source file is e:/mimasuo/bijiaoqi.vhdl.
WARNING:Xst:737 - Found 4-bit latch for signal <a_1>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_2>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_3>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_4>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_5>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_6>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_7>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_8>.
    Found 1-bit register for signal <q>.
    Found 4-bit comparator not equal for signal <$n0009> created at line 41.
    Found 4-bit comparator not equal for signal <$n0010> created at line 42.
    Found 4-bit comparator not equal for signal <$n0011> created at line 43.
    Found 4-bit comparator not equal for signal <$n0012> created at line 44.
    Found 4-bit comparator not equal for signal <$n0013> created at line 45.
    Found 4-bit comparator not equal for signal <$n0014> created at line 46.
    Found 4-bit comparator not equal for signal <$n0015> created at line 47.
    Found 4-bit comparator not equal for signal <$n0016> created at line 48.
    Found 32-bit register for signal <b>.
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred   8 Comparator(s).
Unit <bijiaoqi> synthesized.


Synthesizing Unit <ymq>.
    Related source file is e:/mimasuo/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <fpq01ms>.
    Related source file is e:/mimasuo/fpq01ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 12-bit comparator lessequal for signal <$n0002>.
    Found 12-bit comparator greatequal for signal <$n0007>.
    Found 12-bit comparator lessequal for signal <$n0008>.
    Found 12-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq01ms> synthesized.


Synthesizing Unit <yiwei>.
    Related source file is e:/mimasuo/yiwei.vhdl.
    Found 32-bit register for signal <COUNT>.
    Summary:
	inferred  32 D-type flip-flop(s).
Unit <yiwei> synthesized.


Synthesizing Unit <xzq81>.
    Related source file is e:/mimasuo/xzq81.vhdl.
    Found 4-bit 8-to-1 multiplexer for signal <Q>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <xzq81> synthesized.


Synthesizing Unit <se8>.
    Related source file is e:/mimasuo/SE8.vhdl.
    Found 3-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
Unit <se8> synthesized.


Synthesizing Unit <keyval>.
    Related source file is e:/mimasuo/key.vhdl.
    Found 4-bit register for signal <value>.
    Found 1-bit register for signal <pressed>.
    Found 1-bit register for signal <clr_out>.
    Found 4-bit register for signal <keydrv>.
    Found 4-bit up counter for signal <dd>.
    Found 1-bit register for signal <tpressed>.
    Summary:
	inferred   1 Counter(s).
	inferred  11 D-type flip-flop(s).
Unit <keyval> synthesized.


Synthesizing Unit <fpq10ms>.
    Related source file is e:/mimasuo/fpq10ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 19-bit comparator lessequal for signal <$n0002>.
    Found 19-bit comparator greatequal for signal <$n0007>.
    Found 19-bit comparator lessequal for signal <$n0008>.
    Found 19-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq10ms> synthesized.


Synthesizing Unit <mimasuo>.
    Related source file is e:/mimasuo/mimasuo.vhf.
Unit <mimasuo> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 4
 19-bit up counter                 : 1
 4-bit up counter                  : 1
 12-bit up counter                 : 1
 3-bit up counter                  : 1
# Registers                        : 26
 1-bit register                    : 8
 4-bit register                    : 18
# Latches                          : 9
 7-bit latch                       : 1
 4-bit latch                       : 8
# Comparators                      : 14
 19-bit comparator lessequal       : 2
 19-bit comparator greatequal      : 1
 12-bit comparator lessequal       : 2
 12-bit comparator greatequal      : 1
 4-bit comparator not equal        : 8
# Multiplexers                     : 1
 4-bit 8-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:528 - Multi-source in Unit <bijiaoqi> on signal <cm> not replaced by logic
Signal is stuck at VCC
ERROR:Xst:415 - Synthesis failed
CPU : 3.23 / 5.13 s | Elapsed : 3.00 / 5.00 s
 
--> 

Total memory usage is 55356 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\mimasuo/_ngo -uc YJ.ucf -p
xc2s50-tq144-6 mimasuo.ngc mimasuo.ngd 

WARNING:NgdBuild:257 - Launcher: Could not find the file "e:\mimasuo\mimasuo"
   with extension "ngc" in the search path.  The filename extension will be
   ignored.
ERROR:NgdBuild:28 - Top-level input design file "mimasuo.ngc" cannot be found or
   created. Please make sure the source file exists and is of a recognized
   netlist format (e.g., ngo, ngc, edif, edn, or edf).

Writing NGDBUILD log file "mimasuo.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 52