yiwei.syr

8位密码锁的实现

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: yiwei.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : yiwei.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : yiwei
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : yiwei
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : yiwei.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/mimasuo/yiwei.vhdl in Library work.
Entity <yiwei> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <yiwei> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/yiwei.vhdl line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
WARNING:Xst:819 - E:/mimasuo/yiwei.vhdl line 31: The following signals are missing in the process sensitivity list:
   clr, COUNT.
WARNING:Xst:819 - E:/mimasuo/yiwei.vhdl line 56: The following signals are missing in the process sensitivity list:
   K1, K2, K3, K4, K5, K6, K7, K8.
WARNING:Xst:819 - E:/mimasuo/yiwei.vhdl line 70: The following signals are missing in the process sensitivity list:
   K1, K2, K3, K4, K5, K6, K7, K8.
INFO:Xst:1304 - Contents of register <s> in unit <yiwei> never changes during circuit operation. The register is replaced by logic.
Entity <yiwei> analyzed. Unit <yiwei> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <yiwei>.
    Related source file is E:/mimasuo/yiwei.vhdl.
WARNING:Xst:1780 - Signal <i> is never used or assigned.
WARNING:Xst:737 - Found 4-bit latch for signal <b_1>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_2>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_3>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_4>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_5>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_6>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_7>.
WARNING:Xst:737 - Found 4-bit latch for signal <b_8>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_1>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_2>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_3>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_4>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_5>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_6>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_7>.
WARNING:Xst:737 - Found 4-bit latch for signal <a_8>.
    Found 1-bit register for signal <q>.
    Found 4-bit comparator equal for signal <$n0003>.
    Found 4-bit comparator equal for signal <$n0004>.
    Found 4-bit comparator equal for signal <$n0005>.
    Found 4-bit comparator equal for signal <$n0006>.
    Found 4-bit comparator equal for signal <$n0007>.
    Found 4-bit comparator equal for signal <$n0008>.
    Found 4-bit comparator equal for signal <$n0009>.
    Found 4-bit comparator equal for signal <$n0010>.
    Found 32-bit register for signal <COUNT>.
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred   8 Comparator(s).
Unit <yiwei> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 9
 1-bit register                    : 1
 4-bit register                    : 8
# Latches                          : 16
 4-bit latch                       : 16
# Comparators                      : 8
 4-bit comparator equal            : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <yiwei> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block yiwei, actual ratio is 6.
FlipFlop COUNT_1_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop COUNT_1_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop COUNT_1_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop COUNT_1_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : yiwei.ngr
Top Level Output File Name         : yiwei
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 43

Macro Statistics :
# Registers                        : 9
#      1-bit register              : 1
#      4-bit register              : 8
# Comparators                      : 8
#      4-bit comparator equal      : 8

Cell Usage :
# BELS                             : 25
#      GND                         : 1
#      LUT1                        : 1
#      LUT2                        : 3
#      LUT4                        : 20
# FlipFlops/Latches                : 101
#      FDE                         : 1
#      FDPE                        : 36
#      LD_1                        : 64
# Clock Buffers                    : 3
#      BUFGP                       : 3
# IO Buffers                       : 40
#      IBUF                        : 6
#      OBUF                        : 34
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      56  out of    768     7%  
 Number of Slice Flip Flops:           101  out of   1536     6%  
 Number of 4 input LUTs:                24  out of   1536     1%  
 Number of bonded IOBs:                 40  out of     96    41%  
 Number of GCLKs:                        3  out of      4    75%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
comp                               | BUFGP                  | 32    |
clk                                | BUFGP                  | 37    |
rstcode                            | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 3.234ns (Maximum Frequency: 309.215MHz)
   Minimum input arrival time before clock: 6.592ns
   Maximum output required time after clock: 7.193ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               3.234ns (Levels of Logic = 0)
  Source:            COUNT_7_3 (FF)
  Destination:       COUNT_8_3 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: COUNT_7_3 to COUNT_8_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             4   1.085   1.440  COUNT_7_3 (COUNT_7_3)
     FDPE:D                    0.709          COUNT_8_3
    ----------------------------------------
    Total                      3.234ns (1.794ns logic, 1.440ns route)
                                       (55.5% logic, 44.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              6.592ns (Levels of Logic = 2)
  Source:            comp (PAD)
  Destination:       q (FF)
  Destination Clock: clk rising

  Data Path: comp to q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           33   0.657   3.465  comp_BUFGP (comp_BUFGP)
     LUT1:I0->O            1   0.549   1.035  q_ClkEn_INV1 (q_N97)
     FDE:CE                    0.886          q
    ----------------------------------------
    Total                      6.592ns (2.092ns logic, 4.500ns route)
                                       (31.7% logic, 68.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              7.193ns (Levels of Logic = 1)
  Source:            COUNT_2_3 (FF)
  Destination:       K2<3> (PAD)
  Source Clock:      clk rising

  Data Path: COUNT_2_3 to K2<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             4   1.085   1.440  COUNT_2_3 (COUNT_2_3)
     OBUF:I->O                 4.668          K2_3_OBUF (K2<3>)
    ----------------------------------------
    Total                      7.193ns (5.753ns logic, 1.440ns route)
                                       (80.0% logic, 20.0% route)

=========================================================================
CPU : 3.67 / 6.00 s | Elapsed : 4.00 / 6.00 s
 
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Total memory usage is 57516 kilobytes