xzq81.vhdl

来自「8位密码锁的实现」· VHDL 代码 · 共 58 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity XZQ81 is
    Port ( Q1 : in std_logic_vector(3 downto 0);
           Q2 : in std_logic_vector(3 downto 0);
           Q3 : in std_logic_vector(3 downto 0);
           Q4 : in std_logic_vector(3 downto 0);
		 Q5 : in std_logic_vector(3 downto 0);
           Q6 : in std_logic_vector(3 downto 0);
		 Q7 : in std_logic_vector(3 downto 0);
           Q8 : in std_logic_vector(3 downto 0);
            S : in std_logic_vector(2 downto 0);
		 WX : out std_logic_vector(7 downto 0);
           Q : out std_logic_vector(3 downto 0));
end XZQ81;

architecture Behavioral of XZQ81 is

begin
  process(S)
  begin
	if S="000" then 
	   Q<=Q8;
	   WX<="01111111";
	 elsif S="001" then 
	   Q<=Q7;
	   WX<="10111111";
	 elsif S="010" then 
	   Q<=Q6;
	   WX<="11011111";
	 elsif S="011" then 
	   Q<=Q5;
	   WX<="11101111";
	 elsif S="100" then 
	   Q<=Q4;
	   WX<="11110111";
	 elsif S="101" then 
	   Q<=Q3;
	   WX<="11111011";
	 elsif S="110" then 
	   Q<=Q2;
	   WX<="11111101";
	 elsif S="111" then 
	   Q<=Q1;
	   WX<="11111110";
	 end if;
  end process;

end Behavioral;