s_6.vhdl

来自「简易数字频率计」· VHDL 代码 · 共 28 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity S_6 is
    Port ( CP : in std_logic;
           s: out std_logic_vector(2 downto 0));
end S_6;

architecture Behavioral of S_6 is
begin
  process(CP)
   variable i:std_logic_vector(2 downto 0);
  begin
	  if(CP='1' and CP'event) then
		  i:=i+1;
       end if;
	       s<=i;
 end process;
end Behavioral;