f5p.vhdl

简易数字频率计

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

entity div5freq  is
      port(
            clk   :in std_logic;
            rst   :in std_logic;
            clk4v1:out std_logic;
            clk1v1:out std_logic
                ); 
end div5freq;

architecture behav of div5freq is
        signal  cnt  : std_logic_vector(2 downto 0);
        signal  cnt2 : std_logic_vector(2 downto 0);
        signal  clktmp:std_logic;
        signal  clktmp2:std_logic;
        signal  clktmp3:std_logic;
begin

clk4v1proc: --4v1
        process(clk, rst)
        begin
                if rst = '1' then
                        cnt <= "000";
                        clktmp <= '0';
                elsif clk'event and clk = '1' then
                        if cnt = "100" then
                                clktmp <= not clktmp;
                                cnt <= "000";
                        elsif cnt = "011" then
                                clktmp <= not clktmp;
                                cnt <= cnt + '1';
                        else
                                cnt <= cnt + '1';
                        end if;
                end if;
                clk4v1 <= clktmp;
        end process clk4v1proc;

clk1v1proc:--1v1
	   process(clk, rst) --2v3
        begin
                if rst = '1' then
                        cnt2 <= "000";
                        clktmp2 <= '0';
                elsif clk'event and clk = '1' then
                        if cnt2 = "100" then
                                clktmp2 <= not clktmp2;
                                cnt2 <= "000";
                        elsif cnt2 = "001" then
                                clktmp2 <= not clktmp2;
                                cnt2 <= cnt2 + '1';
                        else
                                cnt2 <= cnt2 + '1';
                        end if;
                end if;
        end process;
        

        process(clk, rst, clktmp2) --sampling at clk's falling
        begin
                if rst = '1' then
                        clktmp3 <= '0';
                elsif clk'event and clk = '0' then
                        clktmp3 <= clktmp2;
                end if;
                clk1v1 <= clktmp3 and  clktmp2;
        end process;                 
        
end behav;