jsq1.vhdl

来自「简易数字频率计」· VHDL 代码 · 共 38 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jsq1 is
    Port ( CLK: in std_logic;
           CLR : in std_logic; 
           EN : in std_logic;
		 COUT: out std_logic;
           D1 : inout std_logic_vector(3 downto 0));
end jsq1;

architecture Behavioral of jsq1 is
begin
 process (CLK,EN,CLR) 
  begin
   if CLR='1'then
         D1<="0000";
   elsif EN='1'then
     if (CLK='1' and CLK'event) then
      if D1="1001" then
	    D1<= "0000";
	    COUT<='1';
      else 
         D1<=D1+1;
	    COUT<='0';
      end if;
    end if;
  end if;
end process;
end Behavioral;