jsq6.vhdl

来自「简易数字频率计」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jsq6 is
    Port ( CIN : in std_logic;
           CLR:in std_logic;
           D6: inout std_logic_vector(3 downto 0));
end jsq6;

architecture Behavioral of jsq6 is
begin
process (CIN,CLR) 
  begin
   if CLR='1'then
         D6<="0000";
   elsif CIN='1' and CIN'event then
       if D6="1001"  then 
	       D6<="0000";
       else 
            D6<= D6+1;
       end if;
   end if;
end process;
end Behavioral;