jsq.syr

简易数字频率计

     MUXCY:CI->O           1   0.042   0.000  XLXI_6_D6_inst_cy_7 (XLXI_6_D6_inst_cy_7)
     MUXCY:CI->O           0   0.042   0.000  XLXI_6_D6_inst_cy_8 (XLXI_6_D6_inst_cy_8)
     XORCY:CI->O           1   0.420   0.000  XLXI_6_D6_inst_sum_7 (XLXI_6_D6_inst_sum_7)
     FDCPE:D                   0.709          XLXI_6_D6_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_4_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_5_D5_5 (FF)
  Destination:       XLXI_5_D5_7 (FF)
  Source Clock:      XLXI_4_COUT:Q rising
  Destination Clock: XLXI_4_COUT:Q rising

  Data Path: XLXI_5_D5_5 to XLXI_5_D5_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_5_D5_5 (XLXI_5_D5_5)
     LUT4_L:I1->LO         2   0.549   0.000  XLXI_5__n00021 (XLXI_5__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_5_D5_inst_cy_5 (XLXI_5_D5_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  XLXI_5_D5_inst_cy_6 (XLXI_5_D5_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  XLXI_5_D5_inst_cy_7 (XLXI_5_D5_inst_cy_7)
     MUXCY:CI->O           0   0.042   0.000  XLXI_5_D5_inst_cy_8 (XLXI_5_D5_inst_cy_8)
     XORCY:CI->O           1   0.420   0.000  XLXI_5_D5_inst_sum_7 (XLXI_5_D5_inst_sum_7)
     FDCPE:D                   0.709          XLXI_5_D5_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_3_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_4_D4_5 (FF)
  Destination:       XLXI_4_D4_7 (FF)
  Source Clock:      XLXI_3_COUT:Q rising
  Destination Clock: XLXI_3_COUT:Q rising

  Data Path: XLXI_4_D4_5 to XLXI_4_D4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_4_D4_5 (XLXI_4_D4_5)
     LUT4_L:I1->LO         2   0.549   0.000  XLXI_4__n00021 (XLXI_4__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_4_D4_inst_cy_5 (XLXI_4_D4_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_D4_inst_cy_6 (XLXI_4_D4_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  XLXI_4_D4_inst_cy_7 (XLXI_4_D4_inst_cy_7)
     MUXCY:CI->O           0   0.042   0.000  XLXI_4_D4_inst_cy_8 (XLXI_4_D4_inst_cy_8)
     XORCY:CI->O           1   0.420   0.000  XLXI_4_D4_inst_sum_7 (XLXI_4_D4_inst_sum_7)
     FDCPE:D                   0.709          XLXI_4_D4_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_3_D3_5 (FF)
  Destination:       XLXI_3_D3_7 (FF)
  Source Clock:      XLXI_2_COUT:Q rising
  Destination Clock: XLXI_2_COUT:Q rising

  Data Path: XLXI_3_D3_5 to XLXI_3_D3_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_D3_5 (XLXI_3_D3_5)
     LUT4_L:I1->LO         2   0.549   0.000  XLXI_3__n00021 (XLXI_3__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_3_D3_inst_cy_5 (XLXI_3_D3_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_D3_inst_cy_6 (XLXI_3_D3_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3_D3_inst_cy_7 (XLXI_3_D3_inst_cy_7)
     MUXCY:CI->O           0   0.042   0.000  XLXI_3_D3_inst_cy_8 (XLXI_3_D3_inst_cy_8)
     XORCY:CI->O           1   0.420   0.000  XLXI_3_D3_inst_sum_7 (XLXI_3_D3_inst_sum_7)
     FDCPE:D                   0.709          XLXI_3_D3_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_1_COUT:Q'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_2_D2_5 (FF)
  Destination:       XLXI_2_D2_7 (FF)
  Source Clock:      XLXI_1_COUT:Q rising
  Destination Clock: XLXI_1_COUT:Q rising

  Data Path: XLXI_2_D2_5 to XLXI_2_D2_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_2_D2_5 (XLXI_2_D2_5)
     LUT4_L:I1->LO         2   0.549   0.000  XLXI_2__n00021 (XLXI_2__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_2_D2_inst_cy_5 (XLXI_2_D2_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  XLXI_2_D2_inst_cy_6 (XLXI_2_D2_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  XLXI_2_D2_inst_cy_7 (XLXI_2_D2_inst_cy_7)
     MUXCY:CI->O           0   0.042   0.000  XLXI_2_D2_inst_cy_8 (XLXI_2_D2_inst_cy_8)
     XORCY:CI->O           1   0.420   0.000  XLXI_2_D2_inst_sum_7 (XLXI_2_D2_inst_sum_7)
     FDCPE:D                   0.709          XLXI_2_D2_7
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               5.114ns (Levels of Logic = 6)
  Source:            XLXI_1_D1_1 (FF)
  Destination:       XLXI_1_D1_3 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_1_D1_1 to XLXI_1_D1_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_1_D1_1 (XLXI_1_D1_1)
     LUT4_L:I1->LO         2   0.549   0.000  XLXI_1__n00021 (XLXI_1__n0002)
     MUXCY:S->O            1   0.659   0.000  XLXI_1_D1_inst_cy_0 (XLXI_1_D1_inst_cy_0)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_D1_inst_cy_1 (XLXI_1_D1_inst_cy_1)
     MUXCY:CI->O           1   0.042   0.000  XLXI_1_D1_inst_cy_2 (XLXI_1_D1_inst_cy_2)
     MUXCY:CI->O           0   0.042   0.000  XLXI_1_D1_inst_cy_3 (XLXI_1_D1_inst_cy_3)
     XORCY:CI->O           1   0.420   0.000  XLXI_1_D1_inst_sum_3 (XLXI_1_D1_inst_sum_3)
     FDCPE:D                   0.709          XLXI_1_D1_3
    ----------------------------------------
    Total                      5.114ns (3.548ns logic, 1.566ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_4_COUT:Q'
Offset:              6.801ns (Levels of Logic = 2)
  Source:            clr (PAD)
  Destination:       XLXI_5_COUT (FF)
  Destination Clock: XLXI_4_COUT:Q rising

  Data Path: clr to XLXI_5_COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            26   0.776   3.150  clr_IBUF (clr_IBUF)
     LUT1:I0->O            4   0.549   1.440  XLXI_2_COUT_N1111 (XLXI_2_COUT_N111)
     FDE:CE                    0.886          XLXI_5_COUT
    ----------------------------------------
    Total                      6.801ns (2.211ns logic, 4.590ns route)
                                       (32.5% logic, 67.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_3_COUT:Q'
Offset:              6.801ns (Levels of Logic = 2)
  Source:            clr (PAD)
  Destination:       XLXI_4_COUT (FF)
  Destination Clock: XLXI_3_COUT:Q rising

  Data Path: clr to XLXI_4_COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            26   0.776   3.150  clr_IBUF (clr_IBUF)
     LUT1:I0->O            4   0.549   1.440  XLXI_2_COUT_N1111 (XLXI_2_COUT_N111)
     FDE:CE                    0.886          XLXI_4_COUT
    ----------------------------------------
    Total                      6.801ns (2.211ns logic, 4.590ns route)
                                       (32.5% logic, 67.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_2_COUT:Q'
Offset:              6.801ns (Levels of Logic = 2)
  Source:            clr (PAD)
  Destination:       XLXI_3_COUT (FF)
  Destination Clock: XLXI_2_COUT:Q rising

  Data Path: clr to XLXI_3_COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            26   0.776   3.150  clr_IBUF (clr_IBUF)
     LUT1:I0->O            4   0.549   1.440  XLXI_2_COUT_N1111 (XLXI_2_COUT_N111)
     FDE:CE                    0.886          XLXI_3_COUT
    ----------------------------------------
    Total                      6.801ns (2.211ns logic, 4.590ns route)
                                       (32.5% logic, 67.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_1_COUT:Q'
Offset:              6.801ns (Levels of Logic = 2)
  Source:            clr (PAD)
  Destination:       XLXI_2_COUT (FF)
  Destination Clock: XLXI_1_COUT:Q rising

  Data Path: clr to XLXI_2_COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            26   0.776   3.150  clr_IBUF (clr_IBUF)
     LUT1:I0->O            4   0.549   1.440  XLXI_2_COUT_N1111 (XLXI_2_COUT_N111)
     FDE:CE                    0.886          XLXI_2_COUT
    ----------------------------------------
    Total                      6.801ns (2.211ns logic, 4.590ns route)
                                       (32.5% logic, 67.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              6.396ns (Levels of Logic = 2)
  Source:            clr (PAD)
  Destination:       XLXI_1_COUT (FF)
  Destination Clock: clk rising

  Data Path: clr to XLXI_1_COUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            26   0.776   3.150  clr_IBUF (clr_IBUF)
     LUT2:I0->O            1   0.549   1.035  XLXI_1__n00031 (XLXI_1__n0003)
     FDE:CE                    0.886          XLXI_1_COUT
    ----------------------------------------
    Total                      6.396ns (2.211ns logic, 4.185ns route)
                                       (34.6% logic, 65.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              7.319ns (Levels of Logic = 1)
  Source:            XLXI_1_D1_2 (FF)
  Destination:       q1<2> (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_1_D1_2 to q1<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_1_D1_2 (XLXI_1_D1_2)
     OBUF:I->O                 4.668          q1_2_OBUF (q1<2>)
    ----------------------------------------
    Total                      7.319ns (5.753ns logic, 1.566ns route)
                                       (78.6% logic, 21.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_1_COUT:Q'
Offset:              7.319ns (Levels of Logic = 1)
  Source:            XLXI_2_D2_6 (FF)
  Destination:       q2<2> (PAD)
  Source Clock:      XLXI_1_COUT:Q rising

  Data Path: XLXI_2_D2_6 to q2<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_2_D2_6 (XLXI_2_D2_6)
     OBUF:I->O                 4.668          q2_2_OBUF (q2<2>)
    ----------------------------------------
    Total                      7.319ns (5.753ns logic, 1.566ns route)
                                       (78.6% logic, 21.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2_COUT:Q'
Offset:              7.319ns (Levels of Logic = 1)
  Source:            XLXI_3_D3_6 (FF)
  Destination:       q3<2> (PAD)
  Source Clock:      XLXI_2_COUT:Q rising

  Data Path: XLXI_3_D3_6 to q3<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_3_D3_6 (XLXI_3_D3_6)
     OBUF:I->O                 4.668          q3_2_OBUF (q3<2>)
    ----------------------------------------
    Total                      7.319ns (5.753ns logic, 1.566ns route)
                                       (78.6% logic, 21.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_3_COUT:Q'
Offset:              7.319ns (Levels of Logic = 1)
  Source:            XLXI_4_D4_6 (FF)
  Destination:       q4<2> (PAD)
  Source Clock:      XLXI_3_COUT:Q rising

  Data Path: XLXI_4_D4_6 to q4<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_4_D4_6 (XLXI_4_D4_6)
     OBUF:I->O                 4.668          q4_2_OBUF (q4<2>)
    ----------------------------------------
    Total                      7.319ns (5.753ns logic, 1.566ns route)
                                       (78.6% logic, 21.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_4_COUT:Q'
Offset:              7.319ns (Levels of Logic = 1)
  Source:            XLXI_5_D5_6 (FF)
  Destination:       q5<2> (PAD)
  Source Clock:      XLXI_4_COUT:Q rising

  Data Path: XLXI_5_D5_6 to q5<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_5_D5_6 (XLXI_5_D5_6)
     OBUF:I->O                 4.668          q5_2_OBUF (q5<2>)
    ----------------------------------------
    Total                      7.319ns (5.753ns logic, 1.566ns route)
                                       (78.6% logic, 21.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_5_COUT:Q'
Offset:              7.319ns (Levels of Logic = 1)
  Source:            XLXI_6_D6_6 (FF)
  Destination:       q6<2> (PAD)
  Source Clock:      XLXI_5_COUT:Q rising

  Data Path: XLXI_6_D6_6 to q6<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   1.085   1.566  XLXI_6_D6_6 (XLXI_6_D6_6)
     OBUF:I->O                 4.668          q6_2_OBUF (q6<2>)
    ----------------------------------------
    Total                      7.319ns (5.753ns logic, 1.566ns route)
                                       (78.6% logic, 21.4% route)

=========================================================================
CPU : 3.14 / 4.67 s | Elapsed : 3.00 / 5.00 s
 
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Total memory usage is 57452 kilobytes