__projnav.log

简易数字频率计

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     125  out of    768    16%  
 Number of Slice Flip Flops:           114  out of   1536     7%  
 Number of 4 input LUTs:               179  out of   1536    11%  
 Number of bonded IOBs:                 11  out of     96    11%  
 Number of TBUFs:                        4  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_18(XLXI_10_I7_0:O)            | NONE(*)(XLXI_6_Q4_0)   | 24    |
XLXN_1(XLXI_1_I3_0:O)              | NONE(*)(XLXI_10_Mtridata_COUNT_EN)| 7     |
XLXI_3_XLXI_5_COUT:Q               | NONE                   | 4     |
XLXI_3_XLXI_4_COUT:Q               | NONE                   | 5     |
XLXI_3_XLXI_3_COUT:Q               | NONE                   | 5     |
XLXI_3_XLXI_2_COUT:Q               | NONE                   | 5     |
XLXI_3_XLXI_1_COUT:Q               | NONE                   | 5     |
XLXN_2(XLXI_2_I3_0:O)              | NONE(*)(XLXI_5_i_0)    | 9     |
clk                                | BUFGP                  | 43    |
XLXI_9__n0001(XLXI_9__n00011:O)    | NONE(*)(XLXI_9_Q_0)    | 7     |
-----------------------------------+------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.541ns (Maximum Frequency: 104.811MHz)
   Minimum input arrival time before clock: 5.082ns
   Maximum output required time after clock: 7.913ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\waitpast\pingche/_ngo -uc
yingjiao.ucf -p xc2s50-tq144-6 pingche.ngc pingche.ngd 

Reading NGO file "D:/waitpast/pingche/pingche.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yingjiao.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41444 kilobytes

Writing NGD file "pingche.ngd" ...

Writing NGDBUILD log file "pingche.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Total Number Slice Registers:     106 out of  1,536    6%
    Number used as Flip Flops:                     82
    Number used as Latches:                        24
  Number of 4 input LUTs:           119 out of  1,536    7%
Logic Distribution:
    Number of occupied Slices:                         128 out of    768   16%
    Number of Slices containing only related logic:    128 out of    128  100%
    Number of Slices containing unrelated logic:         0 out of    128    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          200 out of  1,536   13%
      Number used as logic:                       119
      Number used as a route-thru:                 81
   Number of bonded IOBs:            11 out of     92   11%
      IOB Flip Flops:                               1
      IOB Latches:                                  7
   Number of Tbufs:                   4 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,109
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "pingche_map.mrp" for details.
Completed process "Map".

Mapping Module pingche . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o pingche_map.ncd pingche.ngd pingche.pcf
Mapping Module pingche: DONE



Started process "Place & Route".





Constraints file: pingche.pcf

Loading device database for application Par from file "pingche_map.ncd".
   "pingche" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            11 out of 92     11%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of SLICEs                  128 out of 768    16%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     4 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989a52) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.............................
Phase 5.8 (Checksum:9ab5f4) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file pingche.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 682 unrouted;       REAL time: 0 secs 

Phase 2: 625 unrouted;       REAL time: 3 secs 

Phase 3: 141 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   24   |  0.076     |  0.466      |
+----------------------------+----------+--------+------------+-------------+
|XLXI_3_XLXI_1_COUT          |Low-Skew  |    4   |  0.060     |  4.364      |
+----------------------------+----------+--------+------------+-------------+
|XLXI_3_XLXI_5_COUT          |   Local  |    3   |  0.056     |  2.890      |
+----------------------------+----------+--------+------------+-------------+
|XLXI_3_XLXI_3_COUT          |   Local  |    4   |  0.039     |  2.825      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_2          |   Local  |    7   |  0.363     |  1.981      |
+----------------------------+----------+--------+------------+-------------+
|XLXI_3_XLXI_2_COUT          |   Local  |    4   |  0.324     |  1.418      |
+----------------------------+----------+--------+------------+-------------+
|            XLXN_1          |   Local  |    5   |  0.250     |  2.003      |
+----------------------------+----------+--------+------------+-------------+
|XLXI_3_XLXI_4_COUT          |   Local  |    4   |  0.077     |  2.893      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_18          |   Local  |   12   |  0.430     |  2.102      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_9__n0001          |   Local  |    7   |  0.188     |  2.707      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file pingche.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Mar 20 11:12:00 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module pingche . . .
PAR command line: par -w -intstyle ise -ol std -t 1 pingche_map.ncd pingche.ncd pingche.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/past/pingche/f5q_2.vhdl in Library work.
ERROR:HDLParsers:164 - E:/VHDL/past/pingche/f5q_2.vhdl Line 10. parse error,
   unexpected CLOSEPAR, expecting IDENTIFIER
vhdtdtfi:Declaration (Module f5q_2) not found.
tdtfi(vhdl) completed with errors.
ERROR: vhdtdtfi failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/past/pingche/f5q_2.vhdl in Library work.
ERROR:HDLParsers:164 - E:/VHDL/past/pingche/f5q_2.vhdl Line 10. parse error,
   unexpected CLOSEPAR, expecting IDENTIFIER
vhdtdtfi:Declaration (Module f5) not found.
tdtfi(vhdl) completed with errors.
ERROR: vhdtdtfi failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/past/pingche/f5q_2.vhdl in Library work.
Entity <f5> (Architecture <behav>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/past/pingche/f5q_2.vhdl in Library work.
Architecture behav of Entity f5 is up to date.

==================================================