__projnav.log

简易数字频率计

Place & Route Module pingche . . .
PAR command line: par -w -intstyle ise -ol std -t 1 pingche_map.ncd pingche.ncd pingche.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/waitpast/pingche/kzq.vhdl in Library work.
Entity <KZQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file D:/waitpast/pingche/kz2.vhdl in Library work.
Entity <KZ2> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/waitpast/pingche/jsq1.vhdl in Library work.
Entity <jsq1> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/jsq2.vhdl in Library work.
Entity <jsq2> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/jsq3.vhdl in Library work.
Entity <jsq3> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/jsq4.vhdl in Library work.
Entity <jsq4> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/jsq5.vhdl in Library work.
Entity <jsq5> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/jsq6.vhdl in Library work.
Entity <jsq6> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/fpq1s.vhdl in Library work.
Entity <fpq1s> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/fpq2ms.vhdl in Library work.
Entity <fpq2ms> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/jsq.vhf in Library work.
Entity <jsq> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file D:/waitpast/pingche/s_6.vhdl in Library work.
Entity <S_6> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/scq.vhdl in Library work.
Entity <SCQ> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/xzq.vhdl in Library work.
Entity <SZQ> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/ymq.vhdl in Library work.
Entity <YMQ> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/waitpast/pingche/kz2.vhdl in Library work.
Architecture behavioral of Entity kz2 is up to date.
Compiling vhdl file D:/waitpast/pingche/pingche.vhf in Library work.
Entity <pingche> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pingche> (Architecture <BEHAVIORAL>).
Entity <pingche> analyzed. Unit <pingche> generated.

Analyzing Entity <fpq1s> (Architecture <behavioral>).
Entity <fpq1s> analyzed. Unit <fpq1s> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <jsq> (Architecture <behavioral>).
Entity <jsq> analyzed. Unit <jsq> generated.

Analyzing Entity <jsq1> (Architecture <behavioral>).
Entity <jsq1> analyzed. Unit <jsq1> generated.

Analyzing Entity <jsq2> (Architecture <behavioral>).
Entity <jsq2> analyzed. Unit <jsq2> generated.

Analyzing Entity <jsq3> (Architecture <behavioral>).
Entity <jsq3> analyzed. Unit <jsq3> generated.

Analyzing Entity <jsq4> (Architecture <behavioral>).
Entity <jsq4> analyzed. Unit <jsq4> generated.

Analyzing Entity <jsq5> (Architecture <behavioral>).
Entity <jsq5> analyzed. Unit <jsq5> generated.

Analyzing Entity <jsq6> (Architecture <behavioral>).
Entity <jsq6> analyzed. Unit <jsq6> generated.

Analyzing Entity <s_6> (Architecture <behavioral>).
Entity <s_6> analyzed. Unit <s_6> generated.

Analyzing Entity <scq> (Architecture <behavioral>).
Entity <scq> analyzed. Unit <scq> generated.

Analyzing Entity <szq> (Architecture <behavioral>).
WARNING:Xst:819 - D:/waitpast/pingche/xzq.vhdl line 24: The following signals are missing in the process sensitivity list:
   Q6, Q5, Q4, Q3, Q2, Q1.
Entity <szq> analyzed. Unit <szq> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <kz2> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <b> in unit <kz2> never changes during circuit operation. The register is replaced by logic.
Entity <kz2> analyzed. Unit <kz2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <jsq6>.
    Related source file is D:/waitpast/pingche/jsq6.vhdl.
    Found 4-bit up counter for signal <D6>.
    Summary:
	inferred   1 Counter(s).
Unit <jsq6> synthesized.


Synthesizing Unit <jsq5>.
    Related source file is D:/waitpast/pingche/jsq5.vhdl.
    Found 4-bit up counter for signal <D5>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq5> synthesized.


Synthesizing Unit <jsq4>.
    Related source file is D:/waitpast/pingche/jsq4.vhdl.
    Found 4-bit up counter for signal <D4>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq4> synthesized.


Synthesizing Unit <jsq3>.
    Related source file is D:/waitpast/pingche/jsq3.vhdl.
    Found 4-bit up counter for signal <D3>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq3> synthesized.


Synthesizing Unit <jsq2>.
    Related source file is D:/waitpast/pingche/jsq2.vhdl.
    Found 4-bit up counter for signal <D2>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq2> synthesized.


Synthesizing Unit <jsq1>.
    Related source file is D:/waitpast/pingche/jsq1.vhdl.
    Found 4-bit up counter for signal <D1>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq1> synthesized.


Synthesizing Unit <kz2>.
    Related source file is D:/waitpast/pingche/kz2.vhdl.
    Using one-hot encoding for signal <a>.
    Found 1-bit register for signal <COUNT_CLR>.
    Found 1-bit tristate buffer for signal <COUNT_LOAD>.
    Found 1-bit tristate buffer for signal <COUNT_EN>.
    Found 2-bit register for signal <a>.
    Found 1-bit register for signal <Mtridata_COUNT_EN> created at line 27.
    Found 1-bit register for signal <Mtridata_COUNT_LOAD> created at line 28.
    Found 1-bit register for signal <Mtrien_COUNT_EN> created at line 27.
    Found 1-bit register for signal <Mtrien_COUNT_LOAD> created at line 28.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   2 Tristate(s).
Unit <kz2> synthesized.


Synthesizing Unit <ymq>.
    Related source file is D:/waitpast/pingche/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <szq>.
    Related source file is D:/waitpast/pingche/xzq.vhdl.
Unit <szq> synthesized.


Synthesizing Unit <scq>.
    Related source file is D:/waitpast/pingche/scq.vhdl.
WARNING:Xst:1778 - Inout <Q1> is assigned but never used.
WARNING:Xst:1778 - Inout <Q2> is assigned but never used.
WARNING:Xst:1778 - Inout <Q3> is assigned but never used.
WARNING:Xst:1778 - Inout <Q4> is assigned but never used.
WARNING:Xst:1778 - Inout <Q5> is assigned but never used.
WARNING:Xst:1778 - Inout <Q6> is assigned but never used.
WARNING:Xst:737 - Found 4-bit latch for signal <Q1>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q2>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q3>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q4>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q5>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q6>.
Unit <scq> synthesized.


Synthesizing Unit <s_6>.
    Related source file is D:/waitpast/pingche/s_6.vhdl.
    Found 3-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
Unit <s_6> synthesized.


Synthesizing Unit <jsq>.
    Related source file is D:/waitpast/pingche/jsq.vhf.
Unit <jsq> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is D:/waitpast/pingche/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <fpq1s>.
    Related source file is D:/waitpast/pingche/fpq1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <pingche>.
    Related source file is D:/waitpast/pingche/pingche.vhf.
Unit <pingche> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 9
 4-bit up counter                  : 6
 24-bit up counter                 : 1
 15-bit up counter                 : 1
 3-bit up counter                  : 1
# Registers                        : 15
 1-bit register                    : 14
 2-bit register                    : 1
# Latches                          : 7
 4-bit latch                       : 6
 7-bit latch                       : 1
# Comparators                      : 6
 24-bit comparator lessequal       : 2
 24-bit comparator greatequal      : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
# Tristates                        : 4
 1-bit tristate buffer             : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch a_0 hinder the constant cleaning in the block kz2.
   You should achieve better results by setting this init to 0.
WARNING:Xst:1426 - The value init of the FF/Latch a_1 hinder the constant cleaning in the block kz2.
   You should achieve better results by setting this init to 1.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <pingche> ...

Optimizing unit <szq> ...

Optimizing unit <fpq1s> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <ymq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
WARNING:Xst:382 - Register XLXI_10_Mtrien_COUNT_EN is equivalent to XLXI_10_Mtrien_COUNT_LOAD
Found area constraint ratio of 100 (+ 5) on block pingche, actual ratio is 15.
WARNING:Xst:382 - Register XLXI_10_Mtrien_COUNT_EN is equivalent to XLXI_10_Mtrien_COUNT_LOAD
FlipFlop XLXI_5_i_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================