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简易数字频率计

Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 6
 4-bit up counter                  : 6
# Registers                        : 5
 1-bit register                    : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <jsq> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jsq, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      19  out of    768     2%  
 Number of Slice Flip Flops:            29  out of   1536     1%  
 Number of 4 input LUTs:                20  out of   1536     1%  
 Number of bonded IOBs:                 26  out of     96    27%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_5_COUT:Q                      | NONE                   | 4     |
XLXI_4_COUT:Q                      | NONE                   | 5     |
XLXI_3_COUT:Q                      | NONE                   | 5     |
XLXI_2_COUT:Q                      | NONE                   | 5     |
XLXI_1_COUT:Q                      | NONE                   | 5     |
clk                                | BUFGP                  | 5     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.114ns (Maximum Frequency: 195.542MHz)
   Minimum input arrival time before clock: 6.801ns
   Maximum output required time after clock: 7.319ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq1.vhdl in Library work.
Architecture behavioral of Entity jsq1 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq2.vhdl in Library work.
Architecture behavioral of Entity jsq2 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq3.vhdl in Library work.
Architecture behavioral of Entity jsq3 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq4.vhdl in Library work.
Architecture behavioral of Entity jsq4 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq5.vhdl in Library work.
Architecture behavioral of Entity jsq5 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq6.vhdl in Library work.
Architecture behavioral of Entity jsq6 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/fpq1s.vhdl in Library work.
Architecture behavioral of Entity fpq1s is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/fpq2ms.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq.vhf in Library work.
Architecture behavioral of Entity jsq is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/kzq.vhdl in Library work.
Architecture behavioral of Entity kzq is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/s_6.vhdl in Library work.
Architecture behavioral of Entity s_6 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/scq.vhdl in Library work.
Architecture behavioral of Entity scq is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/xzq.vhdl in Library work.
Architecture behavioral of Entity szq is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/ymq.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/pingche.vhf in Library work.
Entity <pingche> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pingche> (Architecture <BEHAVIORAL>).
Entity <pingche> analyzed. Unit <pingche> generated.

Analyzing Entity <fpq1s> (Architecture <behavioral>).
Entity <fpq1s> analyzed. Unit <fpq1s> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <jsq> (Architecture <behavioral>).
Entity <jsq> analyzed. Unit <jsq> generated.

Analyzing Entity <jsq1> (Architecture <behavioral>).
Entity <jsq1> analyzed. Unit <jsq1> generated.

Analyzing Entity <jsq2> (Architecture <behavioral>).
Entity <jsq2> analyzed. Unit <jsq2> generated.

Analyzing Entity <jsq3> (Architecture <behavioral>).
Entity <jsq3> analyzed. Unit <jsq3> generated.

Analyzing Entity <jsq4> (Architecture <behavioral>).
Entity <jsq4> analyzed. Unit <jsq4> generated.

Analyzing Entity <jsq5> (Architecture <behavioral>).
Entity <jsq5> analyzed. Unit <jsq5> generated.

Analyzing Entity <jsq6> (Architecture <behavioral>).
Entity <jsq6> analyzed. Unit <jsq6> generated.

Analyzing Entity <kzq> (Architecture <behavioral>).
Entity <kzq> analyzed. Unit <kzq> generated.

Analyzing Entity <s_6> (Architecture <behavioral>).
Entity <s_6> analyzed. Unit <s_6> generated.

Analyzing Entity <scq> (Architecture <behavioral>).
Entity <scq> analyzed. Unit <scq> generated.

Analyzing Entity <szq> (Architecture <behavioral>).
WARNING:Xst:819 - f:/zengzhenhu/vhdl/pingche/xzq.vhdl line 24: The following signals are missing in the process sensitivity list:
   Q6, Q5, Q4, Q3, Q2, Q1.
Entity <szq> analyzed. Unit <szq> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <jsq6>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq6.vhdl.
    Found 4-bit up counter for signal <D6>.
    Summary:
	inferred   1 Counter(s).
Unit <jsq6> synthesized.


Synthesizing Unit <jsq5>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq5.vhdl.
    Found 4-bit up counter for signal <D5>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq5> synthesized.


Synthesizing Unit <jsq4>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq4.vhdl.
    Found 4-bit up counter for signal <D4>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq4> synthesized.


Synthesizing Unit <jsq3>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq3.vhdl.
    Found 4-bit up counter for signal <D3>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq3> synthesized.


Synthesizing Unit <jsq2>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq2.vhdl.
    Found 4-bit up counter for signal <D2>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq2> synthesized.


Synthesizing Unit <jsq1>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq1.vhdl.
    Found 4-bit up counter for signal <D1>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq1> synthesized.


Synthesizing Unit <ymq>.
    Related source file is f:/zengzhenhu/vhdl/pingche/ymq.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <szq>.
    Related source file is f:/zengzhenhu/vhdl/pingche/xzq.vhdl.
Unit <szq> synthesized.


Synthesizing Unit <scq>.
    Related source file is f:/zengzhenhu/vhdl/pingche/scq.vhdl.
WARNING:Xst:1778 - Inout <Q1> is assigned but never used.
WARNING:Xst:1778 - Inout <Q2> is assigned but never used.
WARNING:Xst:1778 - Inout <Q3> is assigned but never used.
WARNING:Xst:1778 - Inout <Q4> is assigned but never used.
WARNING:Xst:1778 - Inout <Q5> is assigned but never used.
WARNING:Xst:1778 - Inout <Q6> is assigned but never used.
WARNING:Xst:737 - Found 4-bit latch for signal <Q1>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q2>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q3>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q4>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q5>.
WARNING:Xst:737 - Found 4-bit latch for signal <Q6>.
Unit <scq> synthesized.


Synthesizing Unit <s_6>.
    Related source file is f:/zengzhenhu/vhdl/pingche/s_6.vhdl.
    Found 3-bit up counter for signal <i>.
    Summary:
	inferred   1 Counter(s).
Unit <s_6> synthesized.


Synthesizing Unit <kzq>.
    Related source file is f:/zengzhenhu/vhdl/pingche/kzq.vhdl.
    Found 1-bit register for signal <COUNT_CLR>.
    Found 1-bit tristate buffer for signal <COUNT_LOAD>.
    Found 1-bit tristate buffer for signal <COUNT_EN>.
    Found 2-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_COUNT_EN> created at line 26.
    Found 1-bit register for signal <Mtridata_COUNT_LOAD> created at line 27.
    Found 1-bit register for signal <Mtrien_COUNT_EN> created at line 26.
    Found 1-bit register for signal <Mtrien_COUNT_LOAD> created at line 27.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Tristate(s).
Unit <kzq> synthesized.


Synthesizing Unit <jsq>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq.vhf.
Unit <jsq> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is f:/zengzhenhu/vhdl/pingche/fpq2ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <fpq1s>.
    Related source file is f:/zengzhenhu/vhdl/pingche/fpq1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <pingche>.
    Related source file is f:/zengzhenhu/vhdl/pingche/pingche.vhf.
Unit <pingche> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 10
 4-bit up counter                  : 6
 24-bit up counter                 : 1
 15-bit up counter                 : 1
 2-bit up counter                  : 1
 3-bit up counter                  : 1
# Registers                        : 14
 1-bit register                    : 14
# Latches                          : 7
 4-bit latch                       : 6