scq.vhdl

来自「简易数字频率计」· VHDL 代码 · 共 48 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SCQ is
  port( LOAD:in std_logic;
        D1:in std_logic_vector(3 downto 0);
        D2:in std_logic_vector(3 downto 0);
	   D3:in std_logic_vector(3 downto 0);
	   D4:in std_logic_vector(3 downto 0);
	   D5:in std_logic_vector(3 downto 0);
	   D6:in std_logic_vector(3 downto 0); 
	   Q1:inout std_logic_vector(3 downto 0);
        Q2:inout std_logic_vector(3 downto 0);
	   Q3:inout std_logic_vector(3 downto 0);
	   Q4:inout std_logic_vector(3 downto 0);
	   Q5:inout std_logic_vector(3 downto 0);
	   Q6:inout std_logic_vector(3 downto 0));
end SCQ;

architecture Behavioral of SCQ is
begin
  process(LOAD,D1,D2,D3,D4,D5,D6)
  begin
  if(LOAD='1')then
    Q1<=D1;
    Q2<=D2;
    Q3<=D3;
    Q4<=D4;
    Q5<=D5;
    Q6<=D6;
  else
    Q1<=Q1;
    Q2<=Q2;
    Q3<=Q3;
    Q4<=Q4;
    Q5<=Q5;
    Q6<=Q6;
  end if;
  end process;
end Behavioral;