ymq.vhdl

简易数字频率计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY YMQ IS
  PORT  (
         A: IN std_logic_vector(3 downto 0);
         Q:OUT std_logic_vector(6 downto 0)
	    );
END YMQ;
ARCHITECTURE Behavioral OF YMQ IS
BEGIN 
   PROCESS(A)
   BEGIN 
      CASE A IS
          WHEN"0000"=>Q<="0111111";   --0 
          WHEN"0001"=>Q<="0000110";   --1
          WHEN"0010"=>Q<="1011011";   --2
          WHEN"0011"=>Q<="1001111";   --3
          WHEN"0100"=>Q<="1100110";   --4
          WHEN"0101"=>Q<="1101101";   --5
          WHEN"0110"=>Q<="1111101";   --6
          WHEN"0111"=>Q<="0000111";   --7
          WHEN"1000"=>Q<="1111111";   --8
          WHEN"1001"=>Q<="1100111";   --9
          WHEN  OTHERS =>NULL;   
      END CASE;
   END PROCESS;
END  Behavioral;