jsq5.vhdl

来自「简易数字频率计」· VHDL 代码 · 共 35 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jsq5 is
    Port ( CIN : in std_logic;
		 CLR: in std_logic;
         	 COUT: out std_logic;
           D5 : inout std_logic_vector(3 downto 0));
end jsq5;

architecture Behavioral of jsq5 is
begin
 process (CIN,CLR) 
  begin
   if CLR='1'then
         D5<="0000";
   elsif CIN='1' and CIN'event then
             if D5="1001" then
	         D5<= "0000";
		    COUT<='1';
              else 
              D5<=D5+1;
		    COUT<='0';
             end if;
   end if;
end process;
end Behavioral;