jsq1_tw.ant

简易数字频率计

-- E:\VHDL\PAST\PINGCHE
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Mar 22 18:19:21 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY jsq1_tw IS
END jsq1_tw;

ARCHITECTURE testbench_arch OF jsq1_tw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\vhdl\past\pingche\jsq1_tw.ano";
	COMPONENT jsq1
		PORT (
			CLK : In  std_logic;
			CLR : In  std_logic;
			EN : In  std_logic;
			COUT : Out  std_logic;
			D1 : InOut  std_logic_vector (3 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL CLK : std_logic;
	SIGNAL CLR : std_logic;
	SIGNAL EN : std_logic;
	SIGNAL COUT : std_logic;
	SIGNAL D1 : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : jsq1
	PORT MAP (
		CLK => CLK,
		CLR => CLR,
		EN => EN,
		COUT => COUT,
		D1 => D1
	);

	PROCESS -- clock process for CLK,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_COUT(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",COUT,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, COUT);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_D1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",D1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		CLK <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		CLK <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_COUT(TX_TIME);
		ANNOTATE_D1(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		CLK <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for CLK
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		CLR <= transport '0';
		EN <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION jsq1_cfg OF jsq1_tw IS
	FOR testbench_arch
	END FOR;
END jsq1_cfg;