kz2.vhdl

简易数字频率计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;


entity KZ2 is
  port(CP:in std_logic;
       RST:in std_logic;
	  COUNT_EN:  out std_logic;
	  COUNT_CLR: out std_logic;
	  COUNT_LOAD:out std_logic);
end KZ2;
					
architecture Behavioral of KZ2 is
   signal a:integer range 0 to 2;
   signal b:std_logic;
begin
   process(RST,CP)
   begin
   if RST='1' then
     COUNT_EN<='0';
	COUNT_LOAD<='0';
	COUNT_CLR<='1';
   elsif (CP'event and CP='1') then
          COUNT_CLR<='0';
       if a=1 then
	     a<=0;
       else
		a<=a+1;
	  end if;
	  if b='1' then --------------------------此句赋值实现锁存,始终保持为A=1状态,即一但测出值,则不再变化
	     a<=1;
	  end if;
		case a is
			when 0=>COUNT_EN<='1';
			          COUNT_LOAD<='0';
					 	b<='1'; 
			when 1=>COUNT_EN<='0';
			          COUNT_LOAD<='1';
				
			when others =>COUNT_EN<='Z';
					    COUNT_LOAD<='Z';
		end case;		    
   end if;
   end process;
end Behavioral;